Low latency standard basis GF(2M) multiplier and squarer architectures

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 4, Issue , 1995, Pages 2747-2750

  Jain, Surendra K ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; FLIP FLOP CIRCUITS; LOGIC GATES; POLYNOMIALS;

FINITE FIELD; PARALLEL IN PARALLEL OUT SQUARER; STANDARD BASIS REPRESENTATION; SYSTEM LATENCY;

MULTIPLYING CIRCUITS;

EID: 0028996829     PISSN: 07367791     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)