An Effective Multi-Chip BIST Scheme

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 10, Issue 1-2, 1997, Pages 87-95

  Zorian, Yervant ^a,c,d,e,f,g   Bederr, Hakim ^b,d,h,i  

^a LogicVision   (United States)

^b TEXAS INSTRUMENTS   (France)

^c LogicVision Inc   (United States)

^d LUCENT TECHNOLOGIES   (United States)

^e UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^f MCGILL UNIVERSITY   (Canada)

^g UNIVERSITY OF PENNSYLVANIA   (United States)

^h GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

ⁱ IEEE

Author keywords

Built in self test; DFT; MCM testing

Indexed keywords

ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING;

BUILT IN SELF TEST (BIST); DESIGN FOR TESTABILITY (DFT);

MULTICHIP MODULES;

EID: 0031072239     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/a:1008226715929     Document Type: Article

References (21)

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