Good trellises for ic implementation of viterbi decoders for linear block codes

IEEE Transactions on Communications

Volumn 45, Issue 1, 1997, Pages 52-63

  Moorthy, Hari T ^a   Lin Shu, ^a   Uehara, Gregory T ^a  

^a University of Hawaii at Manoa   (United States)

Author keywords

ACS array architecture; Trellis diagram; Viterbi decoder

Indexed keywords

BINARY CODES; BLOCK CODES; COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; DECODING; VLSI CIRCUITS;

ADD COMPARE SELECT CONNECTIVITY; REED-MULLER CODES; TRELLIS DIAGRAM; VITERBI DECODERS;

TRELLIS CODES;

EID: 0030836168     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/26.554286     Document Type: Article

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