Prototyping the M68060 for concurrent verification

IEEE Design and Test of Computers

Volumn 14, Issue 1, 1997, Pages 34-41

  Kumar, Jainendra ^a,b,c,d  

^a MOTOROLA INC   (United States)

^b SYRACUSE UNIVERSITY   (United States)

^c IEEE   (United States)

^d MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER DEBUGGING; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SOFTWARE; LOGIC GATES; MICROCOMPUTERS; RANDOM PROCESSES; REAL TIME SYSTEMS; SIMULATORS;

CONCURRENT VERIFICATION; DESIGN VERIFICATION; EMULATION PROTOTYPING; HARDWARE EMULATION SYSTEM; IN CIRCUIT EMULATIONS; RANDOM INSTRUCTION SEQUENCE TESTING;

MICROPROCESSOR CHIPS;

EID: 0030737276     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.573363     Document Type: Article

References (5)

1. C. Pixley et al., "Commercial Design Verification: Methodology and Tools," Proc. Int'l Test Conf., IEEE Computer Society Press, Los Alamitos, Calif., 1996.
2. MC68060 Microprocessors User's Manual, M68060UM/AD, Motorola Inc., Austin, Tex., 1994.
3. Programmer's Reference Manual, M68060M/AD, Motorola Inc., Austin, Tex., 1994.
4. J. Kumar, "Emulation Verification Guideline for Motorola Projects," Motorola, Dec. 1995.
5. Mars III User's Guide, Version 3.0, Quickturn Design Systems, Mountain View, Calif., 1993.