A VLSI implementation of an arithmetic coder for image compression

Conference Proceedings of the EUROMICRO

Volumn , Issue , 1997, Pages 591-598

  Peon, Mercedes ^a   Osorio, Roberto R ^a   Bruguera, Javier D ^a  

^a UNIVERSITY OF SANTIAGO DE COMPOSTELA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC CODERS; ARITHMETIC CODING; CUMULATIVE PROBABILITIES; DATA COMPRESSION TECHNIQUES; OPERATING FREQUENCY; REDUNDANT ARITHMETIC; VLSI IMPLEMENTATION;

DATA COMPRESSION; DIGITAL ARITHMETIC; ENCODING (SYMBOLS); IMAGE COMPRESSION; PROBABILITY; STORAGE ALLOCATION (COMPUTER); VLSI CIRCUITS;

INFORMATION TECHNOLOGY; DATA COMPRESSION;

ARITHMETIC CODING;

EID: 0030689481     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1997.617380     Document Type: Conference Paper

References (9)

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