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Volumn , Issue , 1997, Pages 323-330

Low power design of FSMs by state assignment and disabling self-loops

Author keywords

[No Author keywords available]

Indexed keywords

LOW-POWER DESIGN; PATTERN SEQUENCES; PRIMARY INPUTS; STATE ENCODING; SWITCHING ACTIVITIES;

EID: 0030678923     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1997.617303     Document Type: Conference Paper
Times cited : (5)

References (17)
  • 6
    • 3042876212 scopus 로고
    • Re-encoding sequential cir-cuits to reduce power dissipation
    • Napa, April
    • Hachtel,G. et al. : Re-encoding sequential cir-cuits to reduce power dissipation. Int. Workshop on Low-Power Design, Napa, April 1994, pp. 6973.
    • (1994) Int. Workshop on Low-Power Design , pp. 6973
    • Hachtel, G.1
  • 7
    • 0029225009 scopus 로고
    • Logic extraction and fac-torization for low power
    • Iman.S.; Pedram.M.; Logic Extraction and Fac-torization for Low Power. 32th DAC, 1995, pp. 248-253.
    • (1995) 32th DAC , pp. 248-253
    • Iman, S.1    Pedram, M.2
  • 8
    • 0029727335 scopus 로고    scopus 로고
    • State assignment for fsm low power design
    • September 16-20
    • Koegst,M.; Franke,G.; Feske,K.: State Assignment for FSM Low Power Design. EURO-DAC 96, September 16-20, 1996, pp. 28-33.
    • (1996) EURO-DAC 96 , pp. 28-33
    • Koegstm, M.1    Frankeg, G.2    Feskek, K.3
  • 10
    • 84888988029 scopus 로고    scopus 로고
    • April, 8-9, Hamburg, Germany
    • E. I. S.-Workshop, April, 8-9, 1997, Hamburg, Germany, pp. 87-97.
    • (1997) I S.E. Workshop , pp. 87-97
  • 12
    • 0029192470 scopus 로고
    • Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs
    • California, Apr
    • MonteiroJ.; Devadas.S.: Techniques for the Power Estimation of Sequential Logic Circuits Under User-Specified Input Sequences and Programs. Int. Symp. on Low Power Design, Laguna Beach, California, Apr. 1995.
    • (1995) Int. Symp. on Low Power Design, Laguna Beach
    • Monteiro, J.1    Devadas, S.2
  • 14
    • 0027816316 scopus 로고
    • Circuit activity based logic synthesis for low power reliable opera-tions
    • Dec
    • Roy.K.; Prasad,S.C: Circuit Activity Based Logic Synthesis for Low Power Reliable Opera-tions.IEEE Transactions on VLSI Systems, Vol.1, No.4, Dec. 1993, pp. 503-513
    • (1993) IEEE Transactions on VLSI Systems , vol.1 , Issue.4 , pp. 503-513
    • Roy, K.1    Prasad, C.S.2
  • 15
    • 0028693956 scopus 로고
    • A new power estimation technique with application to decomposition of boolean functions for low power
    • Schneider.P.H.; Schlichtmann.U.; Antreich.KJ.: A New Power Estimation Technique with Application to Decomposition of Boolean Functions for Low Power. EURO-DAC 1994, pp. 388-393.
    • (1994) EURO-DAC , pp. 388-393
    • Schneider, P.H.1    Schlichtmann, U.2    Antreich, K.J.3
  • 17
    • 0028565179 scopus 로고
    • Exact and approximate methods for calculating signal and transition probabilities in fsms
    • Tsui,C; Pedram,M.; Despain,A.: Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs. 31th DAC 1994, pp. 18-23.
    • (1994) 31th DAC , pp. 18-23
    • Tsui, C.1    Pedram, M.2    Despain, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.