δ-Bit serial binary addition with linear threshold networks

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 14, Issue 3, 1996, Pages 249-264

  Cotofana, Sorin ^a   Vassiliadis, Stamatis ^a,b  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b IEEE

Author keywords

[No Author keywords available]

Indexed keywords

COST ACCOUNTING; DATA TRANSFER; FEEDFORWARD NEURAL NETWORKS; GATEWAYS (COMPUTER NETWORKS); PERFORMANCE; THRESHOLD ELEMENTS;

LINEAR THRESHOLD NETWORKS;

DATA COMMUNICATION EQUIPMENT;

EID: 0030422213     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00929619     Document Type: Review

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