Correlation between Gate Oxide Reliability and the Profile of the Trench Top Corner in shallow xrench Isolation (STI)

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 747-750

  Park, Tai Su ^a   Shin, Yu Gyun ^a   Lee, Han Sin ^a   Park, Moon Han ^a   Kwon, Sang Dong ^a   Kang, Ho Kyu ^a   Koh, Young Bum ^a   Lee, Moon Yong ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

GATE OXIDE; GATE OXIDE INTEGRITY; GATE OXIDE RELIABILITY; INDUCED DEGRADATION; TRENCH ISOLATION;

GATES (TRANSISTOR); OXIDES;

CHEMICAL POLISHING; CHEMICAL VAPOR DEPOSITION; DEGRADATION; ETCHING; GATES (TRANSISTOR); RELIABILITY; SCANNING ELECTRON MICROSCOPY; SILICA; STRESS CONCENTRATION;

GATE OXIDE RELIABILITY; PLANARIZATION; SHALLOW TRENCH ISOLATION; TRENCH TOP CORNER;

EID: 0030416379     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554088     Document Type: Conference Paper

References (6)

1. [l] P.C. Fazan and V.K. Mathews, "A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMS", IEDM Tech. Dig., pp 57-60, 1993.
2. A. Bryant, W. Hansch, and T. Mii, "Characteristics of CMOS Device Isolation for the ULSI Age", IEDM Tech. Dig., pp 671-674, 1994.
3. A.H. Perera et al., "Trench Isolation for 0.45 pm Active Pitch and Below" IEDM Tech. Dig. pp 679-682 1995.
4. A. Chatterjee et al., "A Shallow Trench Isolation Study for 0.2Y0.18 pm CMOS Technologies and Beyond", Symp. on VLSI Tech., pp 156-157, 1996.
5. H.S. Lee et al., "An Optimized Densification of the Filled Oxide for Quarter Micron Shallow Trench Isolation (STI)", Symp. on VLSI Tech., pp 158-159, 1996.
6. D.H. Ahn et al., "A Highly Practical Modified LOCOS Isolation Technology for the 256 Mbit DRAM", TEDM Tech. Dig., pp 679-682, 1994.