A high-performance architecture with a macroblock-level-pipeline for MPEG-2 coding

Real-Time Imaging

Volumn 2, Issue 6, 1996, Pages 331-340

  Fernández, José M ^a   Moreno, Félix ^a   Meneses, Juan M ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; DATA STORAGE EQUIPMENT; IMAGE COMPRESSION; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; REAL TIME SYSTEMS; REDUCED INSTRUCTION SET COMPUTING;

CROSSBAR NETWORK; MACROBLOCK LEVEL PIPELINE; MOVING PICTURE EXPERTS GROUP; SPECIFIC PURPOSE UNITS;

IMAGE CODING;

EID: 0030415090     PISSN: 10072014     EISSN: None     Source Type: Journal    
DOI: 10.1006/rtim.1996.0034     Document Type: Article

References (30)

1. C-Cube Microsystems (1993) VideoRISC Processor Hardware user's manual.
2. Bursky, D. (1993) Improved DSP ICs eye new horizons. Electronic Design, pp. 69-82.
3. ISO/IEC JTC1/SC29 (1993) Recommendation H.262. Generic coding of moving pictures and associated audio.
4. ISO-IEC JTCI/SC29/WG11 (MPEG93/22b) (1993) Test Model 4.2. Codec Representation of Picture and audio information.
5. Pirsch, P., Demassieux, N. & Gehrke, W. (1995) VLSI architectures for video compression. A survey. Proceedings of the IEEE, 83(2): 220-246.
6. Kasai, R. & Minami, T. (1994) An overview of video coding VLSIs. IEICE Trans, on Electronics, E77-C, (12), 1920-1929.
7. Kim, D. et al. (1994) A real-time encoder using a programmable processor. IEEE Trans. on Consumer Electronics, 40(2): 161-170.
8. Fernández, J.M., Alexandres, S., Sanz, C. & Meneses, J. (1994) Lazo codificador para un sistema MPEG2 en tiempo real. IX Congreso de Diseño de Circuitos Integrados. Las Palmas de Gran Canaria (Spain).
9. Sanz, C., Garrido, M. & Meneses, J. (1996) VLSI architecture for motion estimation using the block-matching algorithm. Proc. of the European Design and Test Conference, pp. 310-314. Paris.
10. Le Gall, D. (1991) MPEG: a video compression standard for multimedia applications. Communications of the ACM. 34(4).
11. Informe Interno. Grupo de Arquitecturas Digitales. Dpto de Ingeniería Electrónica (1994) Proyecto VADIS Eureka-625: Lazo Codificador MPEG-2. ETSIT-UPM.
12. Toyokura, M. et al. (1994) A video DSP with a macroblock-level-pipeline and SIMD type vector-pipeline architecture for MPEG2 CODEC. IEEE Journal of Solid-State Circuits, 29(12).
13. Fernández, J.M., Moreno, F. & Meneses, J. (1995) An approach to the design of RISC core processors for VLSI embedded systems. 21st EUROMICRO Conference, Como (Italy).
14. Gehrke, W., Hoffer, R. & Pirsch, P. (1994) A hierarchical multiprocessor architecture based on meterogeneous processors for video coding applications. Proceedings of the 1994 International Conference on Acoustics, Speech and Signal Processing, 2, pp. 413-416. Adelaide.
15. Wilberg, J. & Camposano, R. (1994) Design of an embedded video compression system. A quantitative approach. ICCD '94.
16. Hwang, K. (1994) Advanced computer architecture: parallelism, scalability, programmability. McGraw Hill Series.
17. Guttag, K. et al. (1992) A single-chip multiprocessor for multimedia: the MVP. IEEE Computer Graphics and Applications, pp. 53-64.
18. Hennessy, J.L. & Patterson, D.A. (1990) Computer architecture. A quantitative approach. Morgan Kaufmann. San Mateo, Cal.
19. Kane, G. & Heinrich, J. (1992) MIPS RISC Architecture. Englewood Cliffs, NJ: Prentice Hall.
20. Bruguera, J. (1995) 2-D DCT using on-line arithmetic. Procettings of the 1995 International Conference on Acoustics, Speech and Signal Processing, 5, pp.3275-3278. Detroit, May 1995.
21. Fernández, J.M. et al. (1995) Diseño de un procesador pipeline para aplicaciones espaciales que realize la DCT bi-dimensional. X Congreso de Diseño de Circuitos Integrados. Zaragoza (Spain), Nov. 1995.
22. Kogge, P.M. (1981) The Architecture of Pipelined Computers. New York: McGraw Hill Book Co., 1981.
23. Steven, G.B., Adams, R.G., Findlay, P.A. & Trainis, S.A. (1992) iHARP: a multiple instruction issue processor. IEE Proceedings-E.
24. Araki, T. et al. (1994) Video DSP Architecture for MPEG2 CODEC. Proceedings of the 1994 International Conference on Acoustics, Speech and Signal Processing, 2, pp.417-420. Adelaide, April 1994.
25. European Silicon Structures (1993) ES2 ECPD1O Library Databook. Datapath Compiler.
26. Design Compiler Reference Manual. V3.O. (1992) Synopsys Inc., Dec.
27. Hailey, S (1995) Deep-submicron technology forces foundry dependence. Electronic Design, 43(7): April 1995.
28. Akiyama, T. et al. (1994) MPEG2 video codec using image compression DSP. IEEE Trans. on Consumer Electronics, 40(3): 466-472.
29. Patterson, D.A. & Hennessy, J.L. (1994) Computer organization and design. The hardware/software interface. Morgan Kaufmann Publishers.
30. Ikeda, M. et al. (1996) A hardware/software concurrent design for a real-time SP@ML video-encoder chip set. Proceedings of the 1996 European Design and Test Conference, pp.320-326. Paris, France, March 1996.