An Efficient Method for Modeling the Effect of Implant Darmage on NMOS Devices Using Effective Profiles and Device Simulation

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 717-720

  Vasanth, K ^a   Saxena, S ^a   McNeil, V ^a   List, S ^a   Davis, J ^a   Kapila, D ^a  

^a Semiconduct Proc Des Ctr T   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE SIMULATIONS; GATE-LENGTH; IMPLANT DAMAGE; MODELING PARAMETERS; NMOS DEVICES; PHENOMENOLOGICAL MODELS; PROFILE SIMULATIONS; SOURCE-DRAIN; SOURCE-DRAIN IMPLANTS; VARIOUS CHANNELS;

MOS DEVICES;

BORON; COMPUTER SIMULATION; CRYSTAL DEFECTS; CURRENT VOLTAGE CHARACTERISTICS; DIFFUSION; INTERFACES (MATERIALS); ION IMPLANTATION;

CHANNEL DOPANT REDISTRIBUTION; IMPLANT DAMAGE; SOURCE DRAIN PROCESSING;

EID: 0030399254     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554081     Document Type: Conference Paper

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