Highly Reliable W/TiN/pn-poly-Si Gate CMOS Technology with Simultaneous Gate and Source/Drain Doping Process

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 447-450

  Wakabayashi, Hitoshi ^a   Andoh, Takeshi ^a   Sato, Kiyoyuki ^a   Yoshida, Kazuyoshi ^a   Miyamoto, Hidenobu ^a   Mogami, Tohru ^a   Kunio, Takemitsu ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRODES; HEAT RESISTANCE; POLYCRYSTALLINE MATERIALS; REFRACTORY METAL COMPOUNDS; SEMICONDUCTOR DOPING; ANNEALING; ELECTRIC VARIABLES MEASUREMENT; GATES (TRANSISTOR); LSI CIRCUITS; SEMICONDUCTING FILMS; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; THERMODYNAMIC STABILITY; TITANIUM NITRIDE;

CMOS DEVICES; CMOS TECHNOLOGY; DOPING PROCESS; DRAIN DOPING; GATE DRAIN; GATE STRUCTURE; LOW RESISTANCE; POLY-SI GATES; SOURCE-DRAIN; THERMALLY STABLE;

TITANIUM NITRIDE; CMOS INTEGRATED CIRCUITS;

GATE ELECTRODE; SOURCE DRAIN DOPING; TITANIUM NITRIDE FILMS; TUNGSTEN FILMS;

EID: 0030386823     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553623     Document Type: Conference Paper

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