Optimization of silicon microstrip detector design for CLEO III

Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

Volumn 383, Issue 1, 1996, Pages 98-103

  Hopman, P I ^a   Alexander, J P ^a   Foland, A D ^a   Kim, P C ^a   Ward, C W ^a  

^a Cornell University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MICROSTRIP DEVICES; OPTIMIZATION; PARTICLE ACCELERATORS; SIGNAL TO NOISE RATIO; SILICON SENSORS; SPURIOUS SIGNAL NOISE;

NOISE OPTIMIZATION; SILICON MICROSTRIP DETECTORS;

PARTICLE DETECTORS;

EID: 0030386336     PISSN: 01689002     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0168-9002(96)00662-6     Document Type: Article

References (6)

1. CLEO III Proposal, CLNS 94/1277 (1994).
2. H. Kagan, these Proceedings (2nd Int. Symp. on Development and Application of Semiconductor Tracking Detectors, Hiroshima, Japan, 1995) Nucl. Instr. and Meth. A 383 (1996) 189.
3. A.D. Poland et al., IEEE Trans. Nucl. Sci. NS-43 (1996) 1746.
4. Hamamatsu Photonics, K.K., 1126-Ichino Cho, Hamamatsu City, Japan; Centre Suisse d'Electronique et de Microtechnique SA, Maladiere 71, CH-2007 Neuchatel, Switzerland.
5. J.P. Alexander et al., Nucl. Instr. and Meth. A 326 (1993) 243.
6. O. Toker et al., Nucl. Instr. and Meth. A 340 (1994) 572.