Novel high speed low skew clock distribution scheme in 0.8 micron CMOS

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 149-152

  Madhavan, Bindu ^a   Sano, Barton ^a   Levi, A F J ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; CMOS INTEGRATED CIRCUITS; DIFFERENTIAL AMPLIFIERS; ELECTRIC LINES; ELECTRIC NETWORK SYNTHESIS; EMITTER COUPLED LOGIC CIRCUITS; FREQUENCIES; PERFORMANCE; SCHEMATIC DIAGRAMS; VLSI CIRCUITS;

CLOCK DISTRIBUTION SCHEME; CLOCK FREQUENCY; CLOCK SIGNALS;

TIMING CIRCUITS;

EID: 0029696337     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)