SCOPUS 정보 검색 플랫폼

Volumn 3, Issue 1, 1992, Pages 63-78

Systolic implementation of digital filters

Author keywords

digital filter implementation; Systolic arrays; VLSI design

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS; COMPUTER SYSTEMS, DIGITAL - REAL TIME OPERATION; SIGNAL PROCESSING - DIGITAL TECHNIQUES;

DIGITAL FILTER IMPLEMENTATION; RASTER SCANNED IMAGES; SYSTOLIC ARRAYS;

ELECTRIC FILTERS, DIGITAL;

EID: 0026819899 PISSN: 09236082 EISSN: 15730824 Source Type: Journal
DOI: 10.1007/BF01941018 Document Type: Article

Times cited : (12)

References (16)

1
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3
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4
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5
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6
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- Why systolic architectures?
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7
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8
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- Prentice Hall, Englewood Cliffs, New Jersey
- (1988) VLSI Array Processors
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9
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10
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- VLSI array architecture for picture processing
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11
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- Addison-Wesley, Reading, MA
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13
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- A systolic realization of 2-D filters
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- Sid-Ahmed, M.A.¹

14
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- S. Sunder, F. El-Guibaly, and A. Antoniou, “Systolic implementation of two-dimensional recursive digital filters,”Proc. IEEE Sym. Circuits and Syst., New Orleans, LA, pp. 1034–1037, May 1990.

15
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- Kluwer Academic Publishers, Boston
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16
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- Realization of multidimensional digital transfer functions
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- Venkateswarlu, T.¹ Eswaran, C.² Antoniou, A.³

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.