A floorplan based methodology for data-path synthesis of sub-micron asics

IEICE Transactions on Information and Systems

Volumn E79-D, Issue 10, 1996, Pages 1389-1395

  Moshnyaga, Vasily G ^a   Tamaru, Keikichi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

A SIC design methodology; High level synthesis

Indexed keywords

ALGORITHMS; DIGITAL FILTERS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC WIRING; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION;

DATA PATH SYNTHESIS; HIGH LEVEL SYNTHESIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030259830     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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