Processor chip design on submicron ASICs

Euro ASIC 1991

Volumn , Issue , 1991, Pages 58-62

  Schettler, H ^a  

^a IBM   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EFFECTIVE CHANNEL LENGTH; MULTI-CHIP; OPERATING FREQUENCY; PROCESSOR CHIPS; SINGLE-CHIP MODULES; SUBMICRON; SUBMICRON TECHNOLOGIES; VLSI CHIP;

INTEGRATED CIRCUIT DESIGN;

EID: 0344685142     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EUASIC.1991.212893     Document Type: Conference Paper

References (9)

1. Einspruch, Gildenblat: "VLSI Electronics Microstructure Science", Vol. 18, 1989 Academic Press, Inc.
2. Neppl F : " Trends und Grenzen der Sub-u-CMOS Technologie" ITG Fachbericht 110, 1989
3. Weste & Eshragian:"Principles of CMOS VLSI Design", 1985 Addison Wesley Publishing Company
4. Schettler, Hajdu, Getzlaff, Loehlein, Starke: "A Mainfraime Processor in CMOS Technology with 0. 5 urn Channel Length. " ISSCC90 Digest
5. Kohn L., Fu S-W. : "A 1. 000. 000 Transistor Microprocessor". ISSCC89 Digest
6. Schettler H. : "Passive Silicon Carrier, Design and Characteristics" ECTC 90, Las Vegas, Mai 1990
7. Miyoshi et al. : " A 50k Gate ECL Array with Substrate Power Supply. " ISSCC89 Digest
8. Petrovick et al. :"A 300k circuit ASIC Logic Family. " ISSCC90 Digest
9. ISSCC90 Discussion Session : "Future Billion-Transistor Systems"