-
1
-
-
0019055071
-
Design of a massively parallel processor
-
BATCHER, K.: 'Design of a massively parallel processor', IEEE Trans., 1980, C-29, pp. 836-840
-
(1980)
IEEE Trans.
, vol.C-29
, pp. 836-840
-
-
Batcher, K.1
-
3
-
-
5944245480
-
Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms
-
PRIVAT, G., PLANET, P., and RENAUDIN, M.: 'Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms'. Proceedings of the international conference on Application specific array processors, 1993
-
(1993)
Proceedings of the International Conference on Application Specific Array Processors
-
-
Privat, G.1
Planet, P.2
Renaudin, M.3
-
4
-
-
0029191890
-
A fine-grain asynchronous VLSI cellular array processor architecture
-
Seattle
-
PRIVAT, G., ROBIN, F., RENAUDIN, M., and EL HASSAN, B.: 'A fine-grain asynchronous VLSI cellular array processor architecture'. Proceedings of the international symposium on Circuits and systems, Seattle, 1995
-
(1995)
Proceedings of the International Symposium on Circuits and Systems
-
-
Privat, G.1
Robin, F.2
Renaudin, M.3
El Hassan, B.4
-
5
-
-
0014496391
-
Chaotic relaxation
-
CHAZAN, D., and MIRANKER, W.: 'Chaotic relaxation', Linear Algebra its Appl., 1969, 2, pp. 199-222
-
(1969)
Linear Algebra Its Appl.
, vol.2
, pp. 199-222
-
-
Chazan, D.1
Miranker, W.2
-
6
-
-
0017958142
-
Asynchronous iterative methods for multiprocessors
-
BAUDET, G.: 'Asynchronous iterative methods for multiprocessors', J. Assoc. Comput. Mach., 1978, 25, (2), pp. 226-244
-
(1978)
J. Assoc. Comput. Mach.
, vol.25
, Issue.2
, pp. 226-244
-
-
Baudet, G.1
-
7
-
-
0024621202
-
Sufficient conditions for the convergence of asynchronous iterations
-
URESIN, A., and DUBOIS, M.: 'Sufficient conditions for the convergence of asynchronous iterations', Parallel Comput., 1989, 10, pp. 83-92
-
(1989)
Parallel Comput.
, vol.10
, pp. 83-92
-
-
Uresin, A.1
Dubois, M.2
-
8
-
-
0026992395
-
Morphological multiscale image segmentation
-
SALEMBIER, P., and SERRA, J.: 'Morphological multiscale image segmentation', Proc. SPIE Vis. Commun. Image Process., 1992. 1818, pp. 620-631
-
(1992)
Proc. SPIE Vis. Commun. Image Process.
, vol.1818
, pp. 620-631
-
-
Salembier, P.1
Serra, J.2
-
9
-
-
0027576716
-
Morphological grayscale reconstruction in image analysis: Applications and efficient algorithms
-
VINCENT, L.: 'Morphological grayscale reconstruction in image analysis: applications and efficient algorithms', IEEE Trans., 1993, IP-2, (2), pp. 176-201
-
(1993)
IEEE Trans.
, vol.IP-2
, Issue.2
, pp. 176-201
-
-
Vincent, L.1
-
10
-
-
33746105585
-
Asynchronous relaxation of morphological operators: A joint architecture-algorithm perspective
-
France
-
ROBIN, F., PRIVAT, G., and RENAUDIN, M.: 'Asynchronous relaxation of morphological operators: a joint architecture-algorithm perspective'. Proceedings of the international workshop on Parallel image analysis, France, 1995
-
(1995)
Proceedings of the International Workshop on Parallel Image Analysis
-
-
Robin, F.1
Privat, G.2
Renaudin, M.3
-
13
-
-
33746113675
-
A minimum power, 100MHz, 12 × 18 + 30 - B multiplier-accumulator operating in asynchronous and synchronous mode
-
Germany
-
RENAUDIN, M., and EL HASSAN, B.: 'A minimum power, 100MHz, 12 × 18 + 30 - b multiplier-accumulator operating in asynchronous and synchronous mode'. Proceedings of the European solid-state circuits conference, Germany, 1994
-
(1994)
Proceedings of the European Solid-state Circuits Conference
-
-
Renaudin, M.1
Hassan B, E.L.2
-
14
-
-
5844241445
-
New self timed rings and their application to division and square root extraction
-
France
-
EL HASSAN, B., GUYOT, A., RENAUDIN, M., and LEVERING, V.: 'New self timed rings and their application to division and square root extraction'. Proceedings of the European solid-state circuits conference, France, 1995, pp. 226-229
-
(1995)
Proceedings of the European Solid-state Circuits Conference
, pp. 226-229
-
-
El Hassan, B.1
Guyot, A.2
Renaudin, M.3
Levering, V.4
-
15
-
-
2342549638
-
Cascode voltage switch logic desian
-
ERDELYI, C.H., GRIFFIN, W.R., and KILMOYER, R.D.: 'Cascode voltage switch logic desian', VLSI Design, 1984, 8, pp. 78-86
-
(1984)
VLSI Design
, vol.8
, pp. 78-86
-
-
Erdelyi, C.H.1
Griffin, W.R.2
Kilmoyer, R.D.3
-
16
-
-
0030191609
-
A new asynchronous pipeline scheme: Application to the design of a self-timed ring divider
-
RENAUDIN, M., EL HASSAN, B., and GUYOT, A.: 'A new asynchronous pipeline scheme: application to the design of a self-timed ring divider', IEEE J. Solid-State Circuits, 1996, 31, (7)
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, Issue.7
-
-
Renaudin, M.1
El Hassan, B.2
Guyot, A.3
-
17
-
-
0022867125
-
Design procedures for differential cascode voltage switch circuits
-
CHU, K.M., and PULFREY, D.: 'Design procedures for differential cascode voltage switch circuits', IEEE J. Solid-State Circuits, 1986, 21, (6), pp. 1082-1087
-
(1986)
IEEE J. Solid-State Circuits
, vol.21
, Issue.6
, pp. 1082-1087
-
-
Chu, K.M.1
Pulfrey, D.2
-
18
-
-
0023549322
-
Metastable behavior in digital systems
-
KLEEMAN, L., and CANTONI, A.: 'Metastable behavior in digital systems', IEEE Des. Test Comput., 1987, 4, pp. 4-19
-
(1987)
IEEE Des. Test Comput.
, vol.4
, pp. 4-19
-
-
Kleeman, L.1
Cantoni, A.2
-
19
-
-
0024070224
-
Q-modules : Internally clocked delay-insensitive modules
-
ROSENBERGER, F.U., MOLNAR, C.E., CHANEY, T.J., and FANG, T.P.: 'Q-modules : internally clocked delay-insensitive modules', IEEE Trans. Computers, 1988, 37, (9)
-
(1988)
IEEE Trans. Computers
, vol.37
, Issue.9
-
-
Rosenberger, F.U.1
Molnar, C.E.2
Chaney, T.J.3
Fang, T.P.4
-
20
-
-
0029191713
-
Asynchronous design methodologies : An overview
-
HAUCK, S.: 'Asynchronous design methodologies : an overview', Proc. IEEE, 1995, 83, (1), pp. 69-93
-
(1995)
Proc. IEEE
, vol.83
, Issue.1
, pp. 69-93
-
-
Hauck, S.1
-
21
-
-
0028369729
-
Synthesis of hazard-free control circuits from asynchronous finite state machines specifications
-
CHU, T.A.: 'Synthesis of hazard-free control circuits from asynchronous finite state machines specifications', J. VLSI Signal Process., 1994, 7, pp. 61-84
-
(1994)
J. VLSI Signal Process.
, vol.7
, pp. 61-84
-
-
Chu, T.A.1
-
22
-
-
0024771230
-
Automatic synthesis of asynchronous circuits from high-level specifications
-
MENG, T.H., BRODERSEN, R.W., and MESSERSCHMITT, D.G.: 'Automatic synthesis of asynchronous circuits from high-level specifications', IEEE Trans., 1989, CAD-8, (11), pp. 1185-1205
-
(1989)
IEEE Trans.
, vol.CAD-8
, Issue.11
, pp. 1185-1205
-
-
Meng, T.H.1
Brodersen, R.W.2
Messerschmitt, D.G.3
|