An improved model for four-terminal junction field-effect transistors

IEEE Transactions on Electron Devices

Volumn 43, Issue 8, 1996, Pages 1309-1311

  Liou, J J ^a   Yue, Y ^a  

^a University of Central Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; GATES (TRANSISTOR); MATHEMATICAL MODELS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; SIGNAL THEORY;

GATE SOURCE TO VOLTAGE; JUNCTION FIELD EFFECT TRANSISTOR; PINCH OFF VOLTAGE; SOURCE TO DRAIN CURRENT;

FIELD EFFECT TRANSISTORS;

EID: 0030214202     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.506786     Document Type: Article

References (6)

1. R. S. C. Cobbold, Theory and Applications of Field-Effect Transistors. New York: Wiley, 1970.
2. T. Taki, "Approximation of junction field-effect transistor characteristics by a hyperbolic function." IEEE J. Sulid-Slate Circuits, vol. SSC-13, p. 724, 1978.
3. J. J. Liou, Advanced Semiconductor Device Physics and Modeling. Boston: Artech House, ch. 4, 1994.
4. W. W. Wong, J. J. Liou, and J. Prentice, "A unified four-terminal junction field-effect transistor model for circuit simulation," Solid Stale Electron., vol. 34, p. 437, 1991.
5. MEDICI Manual, Technology Modeling Associates. Inc.. Palo Alto, CA, ver. 1.1, 1993.
6. R. J. Brew, "The barrier mode behavior of a junction FET at low drain current," Solid-State Electron., vol. 18, p. 1013, 1975.