-
1
-
-
3643137304
-
ASIC Test Cost/Strategy Trade Offs
-
D. L. Wheater, P. Nigh, J. T. Mechler, and L. Lacroix, "ASIC Test Cost/Strategy Trade Offs," Proceedings of the IEEE International Test Conference, 1994, pp. 93-102.
-
(1994)
Proceedings of the IEEE International Test Conference
, pp. 93-102
-
-
Wheater, D.L.1
Nigh, P.2
Mechler, J.T.3
Lacroix, L.4
-
2
-
-
0025403820
-
Boundary-Scan Design Principles for Efficient LSSD ASIC Testing
-
R. W. Bassett, M. E. Turner, J. H. Panner, P. S. Gillis, S. F. Oakland, and D. W. Stout, "Boundary-Scan Design Principles for Efficient LSSD ASIC Testing," IBM J. Res. Develop. 34, 339-354 (1990).
-
(1990)
IBM J. Res. Develop.
, vol.34
, pp. 339-354
-
-
Bassett, R.W.1
Turner, M.E.2
Panner, J.H.3
Gillis, P.S.4
Oakland, S.F.5
Stout, D.W.6
-
3
-
-
0025419938
-
Low Cost Testing of High Density Logic Components
-
April
-
R. W. Bassett, B. J. Butkus, S. L. Dingle, M. R. Faucher, P. S. Gillis, J. H. Panner, J. G. Petrovick, and D. L. Wheater, "Low Cost Testing of High Density Logic Components," IEEE Design & Test of Computers 7, 15-28 (April 1990).
-
(1990)
IEEE Design & Test of Computers
, vol.7
, pp. 15-28
-
-
Bassett, R.W.1
Butkus, B.J.2
Dingle, S.L.3
Faucher, M.R.4
Gillis, P.S.5
Panner, J.H.6
Petrovick, J.G.7
Wheater, D.L.8
-
4
-
-
0030194664
-
Design Methodology for IBM ASIC Products
-
J. J. Engel, T. S. Guzowski, A. Hunt, D. E. Lackey, L. D. Pickup, R. A. Proctor, K. Reynolds, A. M. Rincon, and D. R. Stauffer, "Design Methodology for IBM ASIC Products," IBM J. Res. Develop. 40, 387-406 (1996, this issue).
-
(1996)
IBM J. Res. Develop.
, vol.40
, Issue.THIS ISSUE
, pp. 387-406
-
-
Engel, J.J.1
Guzowski, T.S.2
Hunt, A.3
Lackey, D.E.4
Pickup, L.D.5
Proctor, R.A.6
Reynolds, K.7
Rincon, A.M.8
Stauffer, D.R.9
-
5
-
-
0029219538
-
A Half-Micron CMOS Logic Generation
-
C. W. Koburger III, W. F. Clark, J. W. Adkisson, E. Adler, P. E. Bakeman, A. S. Bergendahl, A. B. Botula, W. Chang, B. Davari, J. H. Givens, H. H. Hansen, S. J. Holmes, D. V. Horak, C. H. Lam, J. B. Lasky, S. E. Luce, R. W. Mann, G. L. Miles, J. S. Nakos, E. J. Nowak, G. Shahidi, Y. Taur, F. R. White, and M. R. Wordeman, "A Half-Micron CMOS Logic Generation," IBM J. Res. Develop. 39, 215-227 (1995).
-
(1995)
IBM J. Res. Develop.
, vol.39
, pp. 215-227
-
-
Koburger III, C.W.1
Clark, W.F.2
Adkisson, J.W.3
Adler, E.4
Bakeman, P.E.5
Bergendahl, A.S.6
Botula, A.B.7
Chang, W.8
Davari, B.9
Givens, J.H.10
Hansen, H.H.11
Holmes, S.J.12
Horak, D.V.13
Lam, C.H.14
Lasky, J.B.15
Luce, S.E.16
Mann, R.W.17
Miles, G.L.18
Nakos, J.S.19
Nowak, E.J.20
Shahidi, G.21
Taur, Y.22
White, F.R.23
Wordeman, M.R.24
more..
-
6
-
-
0027192513
-
A One Million Circuit CMOS ASIC Logic Family
-
R. Gregor, C. Ng, J. Libous, E. Carter, R. Beaudoin, A. Chu, D. Grindel, J. Kinney, M. Lee, L. Mentes, J. Oppold, M. Russel, A. Secor, and G. Yenik, "A One Million Circuit CMOS ASIC Logic Family," Proceedings of the IEEE Custom Integrated Circuits Conference, 1993, pp. 23.1.1-23.1.4.
-
(1993)
Proceedings of the IEEE Custom Integrated Circuits Conference
-
-
Gregor, R.1
Ng, C.2
Libous, J.3
Carter, E.4
Beaudoin, R.5
Chu, A.6
Grindel, D.7
Kinney, J.8
Lee, M.9
Mentes, L.10
Oppold, J.11
Russel, M.12
Secor, A.13
Yenik, G.14
-
8
-
-
0023211754
-
A Versatile VLSI Design System for Combining Gate Array and Standard Cell Circuits on the Same Chip
-
May 4-7
-
R. Hornung, M. Bonneau, B. Waymel, J. Fiore, E. Gould, R. Piro, J. Martin, L. McAllister, and S. Tom, "A Versatile VLSI Design System for Combining Gate Array and Standard Cell Circuits on the Same Chip," presented at the IEEE Custom Integrated Circuits Conference, May 4-7, 1987.
-
(1987)
IEEE Custom Integrated Circuits Conference
-
-
Hornung, R.1
Bonneau, M.2
Waymel, B.3
Fiore, J.4
Gould, E.5
Piro, R.6
Martin, J.7
McAllister, L.8
Tom, S.9
-
9
-
-
0025632433
-
A 300K-Circuit ASIC Logic Family CAD System
-
IBM Microelectronics Division, Essex Junction, Vermont, February
-
J. H. Panner, R. P. Abato, R. W. Bassett, K. M. Carrig, P. S. Gillis, D. J. Hathaway, and T. W. Sehr, "A 300K-Circuit ASIC Logic Family CAD System," Technical Bulletin TR-19.90507, IBM Microelectronics Division, Essex Junction, Vermont, February 1990.
-
(1990)
Technical Bulletin TR-19.90507
-
-
Panner, J.H.1
Abato, R.P.2
Bassett, R.W.3
Carrig, K.M.4
Gillis, P.S.5
Hathaway, D.J.6
Sehr, T.W.7
-
10
-
-
0029537950
-
A High-Performance ROM Compiler for 0.50 μm and 0.36 μm CMOS Technologies
-
September 18-22
-
Robert L. Barry, John D. Chickanosky, Francesco M. Masci, Ronald A. Piro, Steven F. Oakland, Michael R. Ouellette, Douglas W. Kemerer, Maria R. Noack, and William C. Leipold, "A High-Performance ROM Compiler for 0.50 μm and 0.36 μm CMOS Technologies," presented at the IEEE International ASIC Conference and Exhibit, September 18-22, 1995.
-
(1995)
IEEE International ASIC Conference and Exhibit
-
-
Barry, R.L.1
Chickanosky, J.D.2
Masci, F.M.3
Piro, R.A.4
Oakland, S.F.5
Ouellette, M.R.6
Kemerer, D.W.7
Noack, M.R.8
Leipold, W.C.9
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