Design planning for high-performance ASICs

IBM Journal of Research and Development

Volumn 40, Issue 4, 1996, Pages 431-449

  Sayah, J Y ^a   Gupta, R ^a   Sherlekar, D D ^a   Honsinger, P S ^a   Apte, J M ^a   Bollinger, S W ^a   Chen, H H ^a   DasGupta, S ^a   Hsieh, E P ^a   Huber, A D ^a   Hughes, E J ^a   Kurzum, Z M ^a   Rao, V B ^a   Tabtieng, T ^a   Valijan, V ^a   Yang, D Y ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DESIGN AIDS; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT;

CLOCK FREQUENCIES; ELECTRONIC DESIGN AUTOMATION (EDA); HIERARCHICAL DESIGN PLANNING SYSTEMS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030196023     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.404.0431     Document Type: Article

References (17)

1. "ChipBench at a Glance," IBM-EDA Document 0020-5272, IBM Microelectronics Division, Hopewell Junction, NY, April 1995.
2. "EinsTimer Users' Guide and Language Reference," IBM-EDA Document 0020-5261, IBM Microelectronics Division, Hopewell Junction, NY, March 1996.
3. "PREVIEW," http://www.cadence.com/preview.html, Cadence Design Systems, Inc., San Jose, CA 95134, 1996.
4. "Design Planner 3.2, Reference," HDL Systems, Inc., Santa Clara, CA 95054, 1995.
5. IEEE Standards Committee, "Common Delay Calculator User's Guide and Language Reference Manual" (draft of DCL language), IEEE, Piscataway, NJ, 1995.
6. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulating Annealing," Science 220, 671-680 (1983).
7. C. Sechen and A. Sangiovanni-Vincentelli, "The TimberWolf Placement and Routing Package," IEEE J. Solid-State Circuits SC-20, No. 2, 510-522 (1985).
8. W. K. Luk, "A Fast Physical Constraint Generator for Timing-Driven Layout," Proceedings of the 28th ACM/IEEE Design Automation Conference, June 1991, pp. 626-631.
9. Peter S. Hauge, Ravi Nair, and Ellen J. Yoffa, "Circuit Placement for Predictable Performance," Proceedings of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, November 1987, pp. 88-91.
10. H. Youssef and E. Shragowitz, "Timing Constraints for Correct Performance," Proceedings of the IEEE International Conference on Computer-Aided Design, November 1990, pp. 24-27.
11. S. V. Venkatesh, "Hierarchical Timing-Driven Floorplanning and Place and Route Using a Timing Budgeter," Proceedings of the Custom Integrated Circuits Conference, May 1995, pp. 469-472.
12. P. R. O'Brien and T. L. Savarino, "Modeling the Driven-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation," Proceedings of the IEEE International Conference on Computer-Aided Design, November 1989, pp. 24-27.
13. W. C. Elmore, "The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers," J. Appl. Phys. 19, 55-63 (1948).
14. L. T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis," IEEE Trans. Computer-Aided Design 9, 352-366 (1990).
15. D. J. Hathaway, R. R. Habra, E. C. Schanzenbach, and S. J. Rothman, "Circuit Placement, Chip Optimization, and Wire Routing," IBM J. Res. Develop. 40, 453-460 (1996, this issue).
16. N. Deo, Deep Submicron Technology Design Methodology Backgrounder, Synopsys, Inc., Mountain View, CA 94043, June 1995.
17. L. Stok, D. S. Kung, D. Brand, A. D. Drumm, A. J. Sullivan, L. N. Reddy, N. Hieter, D. J. Geiger, H. H. Chao, and P. J. Osier, "BooleDozer: Logic Synthesis for ASICs," IBM J. Res. Develop. 40, No. 4, 407-430 (1996, this issue).