Circuit placement, chip optimization, and wire routing for IBM IC technology

IBM Journal of Research and Development

Volumn 40, Issue 4, 1996, Pages 453-459

  Hathaway, D J ^{a,b,c,d,e,f,g}   Habra, R R ^a,h,i   Schanzenbach, E C ^e   Rothman, S J ^e  

^a IBM MICROELECTRONICS   (United States)

^b DARTMOUTH COLLEGE   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d Ampex Corporation   (United States)

^e Essex Junction Devmt Laboratory ^*

^f IBM   (United States)

^g IEEE

^h East Fishkill Facility ^*

ⁱ Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MICROPROCESSOR CHIPS; OPTIMIZATION;

CHIP OPTIMIZATION; CIRCUIT PLACEMENT; WIRE ROUTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030192673     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.404.0453     Document Type: Article

References (16)

1. J. Y. Sayah, R. Gupta, D. Sherlekar, P. S. Honsinger, S. W. Bollinger, H.-H. Chen, S. DasGupta, E. P. Hsieh, E. J. Hughes, A. D. Huber, Z. M. Kurzum, V. B. Rao, T. Tabtieng, V. Valijan, D. Y. Yang, and J. Apte, "Design Planning for High-Performance ASICs," IBM J. Res. Develop. 40, No. 3, 431-452 (1996, this issue).
2. R. S. Belanger, D. P. Conrady, P. S. Honsinger, T. J. Lavery, S. J. Rothman, E. C. Schanzenbach, D. Sitaram, C. R. Selinger, R. E. DuBois, G. W. Mahoney, and G. F. Miceli, "Enhanced Chip/Package Design for the IBM ES/9000," Proceedings of the IEEE International Conference on Computer Design, 1991, pp. 544-549.
3. J. H. Panner, R. P. Abato, R. W. Bassett, K. M. Carrig, P. S. Gillis, D. J. Hathaway, and T. W. Sehr, "A Comprehensive CAD System for High-Performance 300K-Circuit ASIC Logic Chips," IEEE J. Solid-State Circuits 26, No. 3, 300-309 (March 1991).
4. R. F. Lembach, J. F. Borkenhagen, J. R. Elliot, and R. A. Schmidt, "VLSI Design Automation for the Application System/400," Proceedings of the IEEE International Conference on Computer Design, 1991, pp. 444-447.
5. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by Simulated Annealing," Science 220, No. 4598, 671-680 (May 1983).
6. K. J. Antreich, F. M. Johannes, and F. H. Kirsch, "A New Approach for Solving the Placement Problem Using Force Models," Proceedings of the IEEE Symposium on Circuits and Systems, 1982, pp. 481-486.
7. R.-S. Tsay, E. S. Kuh, and C.-P. Hsu, "PROUD: A Fast Sea-of-Gates Placement Algorithm," Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988, pp. 318-323.
8. K. Narayan, "Clock System Design for High Speed Integrated Circuits," IEEE/ERA Wescon/92 Conference Record, 1992, pp. 21-24.
9. H. B. Bakoglu, J. T. Walker, and J. D. Meindl, "A Symmetric Clock Distribution Tree and Optimized High Speed Interconnections for Reduced Clock Skew in ULSI and WSI Circuits," Proceedings of the IEEE International Conference on Computer Design, 1986, pp. 118-122.
10. K. M. Carrig, D. J. Hathaway, K. W. Lallier, J. H. Panner, and T. W. Sehr, "Method and Apparatus for Making a Skew-Controlled Signal Distribution Network," U.S. Patent 5, 339, 253, 1994.
11. R.-S. Tsay, "An Exact Zero-Skew Clock Routing Algorithm," IEEE Trans. Computer-Aided Design 14, No. 12, 242-249 (February 1993).
12. K. D. Boese and A. B. Kahng, "Zero-Skew Clock Routing Trees with Minimum Wirelength," Proceedings of the Fifth Annual IEEE International ASIC Conference and Exhibit, 1992, pp. 17-21.
13. S. Pullela, N. Menezes, J. Omar, and L. T. Pillage, "Skew and Delay Optimization for Reliable Buffered Clock Trees," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1993, pp. 556-562.
14. R. Kent Dybvig, The Scheme Programming Language, Prentice-Hall, Inc., Englewood Cliffs, NJ, 1987.
15. C. W. Koburger III, W. F. Clark, J. W. Adkisson, E. Adler, P. E. Bakeman, A. S. Bergendahl, A. B. Botula, W. Chang, B. Davari, J. H. Givens, H. H. Hansen, S. J. Holmes, D. V. Horak, C. H. Lam, J. B. Lasky, S. E. Luce, R. W. Mann, G. L. Miles, J. S. Nakos, E. J. Nowak, G. Shahidi, Y. Taur, F. R. White, and M. R. Wordeman, "A Half-Micron CMOS Logic Generation," IBM J. Res. Develop. 39, No. 1/2, 215-227 (January/March 1995).
16. P. C. Elmendorf, "KWIRE: Multiple-Technology, User-Reconfigurable Wiring Tool for VLSI," IBM J. Res. Develop. 28, No. 5, 603-612 (September 1984).