FsmTest: Functional test generation for sequential circuits

Integration, the VLSI Journal

Volumn 20, Issue 3, 1996, Pages 303-325

  Buonanno, G ^a   Fummi, F ^a   Sciuto, D ^a   Lombardi, F ^b  

^a POLITECNICO DI MILANO   (Italy)

^b Texas A and M University   (United States)

Author keywords

Distinguishing sequences; Functional testing; Test pattern generation

Indexed keywords

ALGORITHMS; CONTROL SYSTEM SYNTHESIS; FINITE AUTOMATA; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MATHEMATICAL MODELS;

FINITE STATE MACHINE; FUNCTIONAL TESTING; TEST PATTERN GENERATION;

SEQUENTIAL CIRCUITS;

EID: 0030193964     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/0167-9260(96)00006-5     Document Type: Article

References (28)

1. V.D. Agrawal, K.T. Cheng and P. Agrawal, A directed search method for test generation using a concurrent simulator, IEEE Trans. CAD of ICs 8 (1989) 131-138.
2. M.J. Bending, HITEST - A knowledge-based test generation system, IEEE Design Test Comput. 1 (1984) 83-93.
3. H-K.T. Ma et al., Test generation for sequential circuits, IEEE Trans, on CAD 7(10) (1988) 1081-1093.
4. W-T. Cheng and T.J. Chakraborty, Gentest: an automatic test-generation system for sequential circuits, IEEE Comput. 22 (10) (1989) 43-49.
5. T. Niermann and J.H. Patel, HITEC/PROOFS: a test generation and fault simulation system for sequential circuits, Proc. ITC 90.
6. A. Ghosh, S. Devadas and A.K. Newton, Test generation and verification for highly sequential circuits, IEEE Trans. CAD 10(5) (1991) 652-667.
7. S. Devadas, A. Ghosh and R. Newton, Test generation and verification for highly sequential circuits, IEEE Trans. CAD 10(5) (1991) 652-667.
8. T.P. Kelsey and K.K. Saluja, Fast test generation for sequential circuits, Proc. Internat. Conf. Computer Aided Design (1989) 354-357.
9. K.T. Cheng and D.D. Agrawal, A partial scan method for sequential circuits with feedback. IEEE Trans. Comput. C-39(4) (1990) 544-548.
10. H. Gundlach, B. Koch and K. Muller Glaser, On the selection of a partial scan path with respect to target faults, EDAC '91.
11. S. Devadas, Optimizing interacting finite state machines using sequential don't cares, IEEE Trans. CAD 10(12) (1991).
12. H. Savoj, R. Brayton and H.J. Touati, Extracting local don't cares for network optimization, Proc. DAC '92, pp. 514-517.
13. K.-T. Cheng and J.-Y. Jou, Functional test generation for finite state machines, Proc. ITC 90, IEEE, pp. 162-168.
14. R. Miller and S. Paul, Generating minimal length test sequences for conformance testing of communication protocols, Symp. on Protocol Specification, Testing and Verification, IEEE (1991).
15. I. Pomeranz and S.M. Reddy, On achieving a complete fault coverage for sequential machines using the transition fault model, Proc. Design Autom. Conf. (1991) pp. 341-346.
16. I. Pomeranz and S.M. Reddy, The multiple observation time test strategy, IEEE Trans. Comput. 41 (1992) 627-637.
17. M. Karam and G. Saucier, Functional versus random test generation for sequential circuits, J. Electronic Testing: Theory and Applications 4 (1993) pp. 33-41.
18. F.C. Hennie, Fault detecting experiments for sequential circuits, Proc. 5th Ann. Symp. on Switching Circuit Theory and Logical Design (1964) pp. 95-110.
19. A. Aho, A.T. Dahbura, D. Lee and M. Umit Uyar, An optimization technique for protocol conformance test generation based on UIO sequences and Rural Chinese Postman Tours, in: Protocol Specification, Testing and Verification, Vol. VIII (North-Holland, Amsterdam, 1988) pp. 75-86.
20. Y.-N. Shen, F. Lombardi and A.T. Dahbura, Protocol conformance testing by multiple UIO sequence, in: Protocol Specification, Testing and Verification, Vol. IX (North-Holland, Amsterdam, 1990) pp. 131-143.
21. K.K. Sabnani and A.T. Dahbura, A protocol test generation procedure, Computer Networks 15(4) (1988) 285-297.
22. M.S. Chen, Y. Choi and A. Kershenbaum, Approaches utilizing segment overlap to minimize test sequences, Symp. on Protocol Specification, Testing and Verification (1990).
23. R. Bryant, Graph-based algorithms for boolean function manipulation, IEEE Trans. Comput. C-35 (1986).
24. K.-T. Cheng and J.-Y. Jou, A single-state-transition fault model for sequential machines, Proc. ICCAD 90, IEEE, pp. 226-229.
25. F. Lombardi, D. Sciuto and Y.-N. Shen, Evaluation and improvement of fault coverage for verification and validation of protocols, Proc. Internat. Symp. on Parallel and Distributed Processing (1990) 200-207.
26. M.C. Paull and S.H. Unger, Minimizing the number of states in incompletely specified sequential switching circuits, IRE Trans. Electronic Comput. EC-8 (1959) 356-367.
27. SIS: A System for Sequential Circuit Synthesis, Electronics Research Lab., Mem. No. UCB/ERL M92/41, Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, 1992.
28. System HILO Reference Manual, GenRad Inc. (1988).