A 2.5-Gb/s 15-mW clock recovery circuit

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 4, 1996, Pages 472-480

  Razavi, Behzad ^a,b,c  

^a LUCENT TECHNOLOGIES   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c IEEE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA PROCESSING; INTEGRATED CIRCUIT LAYOUT; OPTICAL COMMUNICATION; PHASE SHIFT; PHOTODETECTORS; SIGNAL DETECTION; SIGNAL RECEIVERS; VARIABLE FREQUENCY OSCILLATORS; VLSI CIRCUITS;

CLOCK RECOVERY CIRCUIT; FIBER OPTIC RECEIVERS; FREQUENCY DETECTION; PHASE DETECTION; TRANSIMPEDANCE AMPLIFIER;

TIMING CIRCUITS;

EID: 0030125319     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.499722     Document Type: Article

References (13)

1. M. Soyuer, "A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technology," IEEE J. Solid-State Circuits, vol. 28, pp. 1310-1313, Dec. 1993.
2. D. Richman, "Color-carrier reference phase synchronization accuracy in NTSC color television," Proc. IRE, vol. 42, pp. 106-133, Jan. 1954.
3. J. A. Bellisio, "A new phase-locked loop timing recovery method for digital regenerators," in IEEE Int. Conf. Rec., vol. 1, June 1976, pp. 10-17.
4. H. Ransijn and P. O'Connor, "A PLL-based 2.5-Gb/s clock and data regenerator IC," IEEE J. Solid-State Circuits, vol. 26, pp. 1337-1344, Oct. 1991.
5. F. B. McCormick et al., "Five-stage free-space optical switching network with field-effect transistor self-electrooptic-effect-device smart-pixel arrays," Applied Optics, vol. 33, pp. 1601-1618, Mar. 10, 1994.
6. S. K. Shanmugam, Digital and Analog Communication Systems. New York: Wiley, 1979.
7. B. Razavi, "Design of monolithic phase-locked loops and clock recovery circuits - a tutorial," in Monolithic Phase-Locked Loops and Clock Recovery Circuits, B. Razavi, Ed. Piscataway, NJ: IEEE Press, 1996.
8. R. R. Cordell et al., "A 50 MHz phase- and frequency-locked loop," IEEE J. Solid-State Circuits, vol. SC-14, pp. 1003-1009, Dec. 1979.
9. A. Pottbacker and U. Langmann, "An 8 GHz silicon bipolar clock recovery and data regenerator IC," IEEE J. Solid-State Circuits, vol. 29, pp. 1572-1576, Dec. 1994.
10. I. A. Young, J. K. Greason, and K. L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors," IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.
11. D. Wolaver, Phase-Locked Loop Circuit Design. Englewood Cliffs, NJ: Prentice-Hall, 1991.
12. D. G. Messerschmitt, "Frequency detectors for PLL acquisition in timing and carrier recovery," IEEE Trans. Commun., vol. COM-27, pp. 1288-1295, Sept. 1979.
13. J. Sung et al., "BEST2 - A high performance super self-aligned 3V/5V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications," in Proc. IEEE CICC, May 1994, pp. 15-18.