Trends in high-speed DRAM architectures

IEICE Transactions on Electronics

Volumn E79-C, Issue 4, 1996, Pages 472-480

  Kumanoya, Masaki ^a   Ogawa, Toshiyuki ^a   Konishi, Yasuhiro ^a   Dosaka, Katsumi ^a   Shimotori, Kazuhiro ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

Bandwidth bottleneck; DRAM; Graphics memory; High speed dram; High speed i o interface; Main memory; Performance comparison; Performance gap; Review; System integration; Unified memory

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER GRAPHICS; INTERFACES (COMPUTER); MULTIPROCESSING SYSTEMS;

BANDWIDTH BOTTLENECK; DYNAMIC RANDOM ACCESS MEMORY (DRAM); GRAPHICS MEMORY; PERFORMANCE GAP; SYSTEM INTEGRATION;

RANDOM ACCESS STORAGE;

EID: 0030121659     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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