Improvement of the majority gate algorithm for grey scale dilation/erosion

Electronics Letters

Volumn 32, Issue 9, 1996, Pages 806-807

  Gasteratos, A ^a   Andreadis, I ^a   Tsalides, P ^a  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

Author keywords

Computer vision; Mathematical morphology

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; IMAGE PROCESSING; MATHEMATICAL MORPHOLOGY; MATHEMATICAL OPERATORS; SYSTOLIC ARRAYS;

GREY SCALE MORPHOLOGICAL OPERATIONS; MAJORITY GATE ALGORITHM;

COMPUTER VISION;

EID: 0030120631     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19960529     Document Type: Article

References (6)

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2. STERNBERG, S.R.: 'Grayscale morphology', Comput. Vis. Graph. Image Process., 1986, 35, (3), pp. 333-355
3. DUFF, M.J.B., and FOUNTAIN, T.J., 'Cellular logic image processing' (Academic Press, London, 1986)
4. ANDREADIS, I., GASTERATOS, A., and TSALIDES, P.: 'An ASIC for fast grey-scale dilation', to be published in Microprocess. Microsyst.
5. LEE, C.L., and JEN, C.W.: 'Bit-sliced median filter design based on majority gate', IEE Proc. G, 1992, 139, (1), pp. 63-71
6. CHEN, C.H., and YANG, D.L.: 'Realisation of morphological operations', IEE Proc., Circuits Devices Syst., 1995, 142, (6), pp. 364-368