An ASIC for fast grey-scale dilation

Microprocessors and Microsystems

Volumn 20, Issue 2, 1996, Pages 89-95

  Andreadis, I ^a   Gasteratos, A ^a   Tsalides, Ph ^a  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

Author keywords

ASIC; Mathematical morphology; VLSI

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER VISION; IMAGE PROCESSING; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MORPHOLOGY; PERFORMANCE; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

EUROPEAN SILICON STRUCTURE; GREY SCALE DILATION; GREY SCALE IMAGES; PIXEL IMAGES; STRUCTURING ELEMENTS; THRESHOLD DECOMPOSITION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030125468     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/0141-9331(95)01069-6     Document Type: Article

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