Evaluation of the Upset Risk in CMOS SRAM Through Full Three Dimensional Simulation

IEEE Transactions on Nuclear Science

Volumn 42, Issue 6, 1995, Pages 1789-1796

  Moreau, Yves ^a   Duzellier, Sophie ^b   Gasiot, Jean ^a  

^a UNIVERSITÉ MONTPELLIER II   (France)

^b ONERA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; MATHEMATICAL MODELS; RADIATION EFFECTS;

BIT ERROR RISK; INCIDENCE ANGLE; INCIDENT HEAVY ION; STATIC RANDOM ACCESS MEMORY (SRAM); UPSET RISK;

RANDOM ACCESS STORAGE;

EID: 0029516457     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.488780     Document Type: Article

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