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Volumn 16, Issue 9, 1995, Pages 402-404

A New High-Performance Lateral Insulated Gate Bipolar Transistor Formed On Quasi-SOI

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC CONDUCTIVITY; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; OXIDES; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THIN FILM DEVICES;

EID: 0029379175     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.406802     Document Type: Article
Times cited : (6)

References (11)
  • 1
    • 0021757034 scopus 로고
    • Lateral RESURFed COMFET
    • M. Darwish and K. Board, “Lateral RESURFed COMFET,” Electron Lett., vol. 20, pp. 519–520, 1984.
    • (1984) Electron Lett. , vol.20 , pp. 519-520
    • Darwish, M.1    Board, K.2
  • 2
    • 0022329893 scopus 로고
    • Lateral insulated gate transistor with improved latching characteristics
    • A. Robinson, D. Pattanayak, M. Adler, B. J. Baliga, and E. Wildi, “Lateral insulated gate transistor with improved latching characteristics,” IEDM Tech. Dig., pp. 744–747, 1985.
    • (1985) IEDM Tech. Dig. , pp. 744-747
    • Robinson, A.1    Pattanayak, D.2    Adler, M.3    Baliga, B.J.4    Wildi, E.5
  • 3
    • 0023599847 scopus 로고
    • Latching in lateral insulated gate bipolar transistors
    • T. P. Chow, D. Pattanayak, M. Adler, and B. J. Baliga, “Latching in lateral insulated gate bipolar transistors,” IEDM Tech. Dig., pp. 774–777, 1987.
    • (1987) IEDM Tech. Dig. , pp. 774-777
    • Chow, T.P.1    Pattanayak, D.2    Adler, M.3    Baliga, B.J.4
  • 5
    • 0026960387 scopus 로고
    • Novel high-voltage silicon-on-insulator MOSFETs
    • Q. Lu, P. Ratnam, and C. A. T. Salama, “Novel high-voltage silicon-on-insulator MOSFETs,” Solid-State Electron., vol. 13, pp. 1745–1750, 1992.
    • (1992) Solid-State Electron. , vol.13 , pp. 1745-1750
    • Lu, Q.1    Ratnam, P.2    Salama, C.A.T.3
  • 8
    • 0027307187 scopus 로고    scopus 로고
    • SOI LIGBT devices with dual P- well implant for improved latching characteristics
    • D. R. Disney and J. D. Plummer, “SOI LIGBT devices with dual P- well implant for improved latching characteristics,” in Proc.ISPSD'93, pp. 254–258.
    • Proc. ISPSD'93 , pp. 254-258
    • Disney, D.R.1    Plummer, J.D.2
  • 9
    • 33747673413 scopus 로고
    • Quasi-SOI MOSFET using selective epitaxy and polishing
    • C. T. Nguyen, S. C. Kuehne, P. Renteln, and S. S. Wong, “Quasi-SOI MOSFET using selective epitaxy and polishing,” in IEDM Tech, Dig., 1992, pp. 341–344.
    • (1992) IEDM Tech, Dig. , pp. 341-344
    • Nguyen, C.T.1    Kuehne, S.C.2    Renteln, P.3    Wong, S.S.4
  • 11
    • 0029252390 scopus 로고
    • A trench-gate silicon-on-insulator lateral insulated gate bipolar transistor with the p+ cathode well
    • B.-H. Lee, C.-M. Yun, D.-S. Byeon, M.-K. Han, and Y. I. Choi, “A trench-gate silicon-on-insulator lateral insulated gate bipolar transistor with the p+ cathode well,” Jpn. J. Applied Physics, vol. 34, pp. 854–859, 1995.
    • (1995) Jpn. J. Applied Physics , vol.34 , pp. 854-859
    • Lee, B.-H.1    Yun, C.-M.2    Byeon, D.-S.3    Han, M.-K.4    Choi, Y.I.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.