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Volumn 44, Issue 8, 1995, Pages 971-982

A Systematic Methodology for the Design of High Performance Recursive Digital Filters

Author keywords

computer arithmetic; design methodology; fine grained pipelining; most significant bit first arithmetic; multiply accumulate algorithms; Recursive digital filers; VLSI architectures

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; MATHEMATICAL OPERATORS; PIPELINE PROCESSING SYSTEMS; RECURSIVE FUNCTIONS; TRANSFER FUNCTIONS; VLSI CIRCUITS;

EID: 0029358071     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.403713     Document Type: Article
Times cited : (14)

References (31)
  • 2
    • 5544302589 scopus 로고
    • Bit level systolic architectures for high performance IIR filtering
    • S.C. Knowles, J.G. McWhirter, R.F. Woods, and J.V. McCanny, “Bit level systolic architectures for high performance IIR filtering,” J. VLSI Signal Processing, vol. 1, pp. 9-24, 1989.
    • (1989) J. VLSI Signal Processing , vol.1 , pp. 9-24
    • Knowles, S.C.1
  • 3
    • 0024700229 scopus 로고
    • Pipeline interleaving and parallelism in recursive digital filters-Part 1: Pipelining using scattered look-ahead and decomposition
    • Speech, and Signal Processing
    • K.K. Parhi and D.G. Messerschmitt, “Pipeline interleaving and parallelism in recursive digital filters-Part 1: Pipelining using scattered look-ahead and decomposition,” IEEE Trans. Acoustics, Speech, and Signal Processing, vol. 37, no. 7, pp. 1,099 - 1,117, July 1989.
    • (1989) IEEE Trans. Acoustics , vol.37 , Issue.7 , pp. 1,099-1,117
    • Parhi, K.K.1    Messerschmitt, D.G.2
  • 4
    • 84889537036 scopus 로고
    • On the use of most significant bit first arithmetic in the design of high performance DSP chips
    • J.V. McCanny, “On the use of most significant bit first arithmetic in the design of high performance DSP chips,” Algorithms and Parallel VLSI Architectures, Y. Robert and P. Quinton, eds., pp. 243-259, Elsevier Press, 1992.
    • (1992) Algorithms and Parallel VLSI Architectures
    • McCanny, J.V.1
  • 6
    • 0025665866 scopus 로고
    • A new faster and simpler systolic structure for IIR filters
    • M. Lapointe, P. Fortier, and H.T. Huynh, “A new faster and simpler systolic structure for IIR filters,” Proc. IEEE Int'l Conf. Circuits and Systems, pp. 1,227-1,230,1990.
    • (1990) Proc. IEEE Int'l Conf. Circuits and Systems , pp. 1,227-1,230
    • Lapointe, M.1    Fortier, P.2
  • 7
    • 0024792908 scopus 로고
    • Most-significant-digit-first and online arithmetic approaches for the design of recursive filters
    • M.D. Ercegovac and T. Lang, “Most-significant-digit-first and online arithmetic approaches for the design of recursive filters,” Proc. 23rd Asilomar Conf. Circuits, Signals, and Computers, pp. 7-11, 1989.
    • (1989) Proc. 23rd Asilomar Conf. Circuits
    • Ercegovac, M.D.1    Lang, T.2
  • 8
    • 0026946025 scopus 로고
    • High performance VLSI architectures for wave digital filtering
    • R.J. Singh and J.V. McCanny, “High performance VLSI architectures for wave digital filtering,” J. VLSI Signal Processing, vol 4, pp. 269-278, 1992
    • (1992) J. VLSI Signal Processing
    • Singh, R.J.1    McCanny, J.V.2
  • 10
    • 84938154470 scopus 로고
    • The design of a highly pipelined second order IIR filter chip
    • Aug.
    • O.C. McNally, J.V. McCanny, and R.F. Woods, “The design of a highly pipelined second order IIR filter chip,” VLSI ‘91, pp. 2.2.1-2.1.10, Edinburgh, Aug. 1991.
    • (1991) VLSI ‘91
    • McNally, O.C.1
  • 11
    • 0037879394 scopus 로고
    • A high performance first order IIR Filter chip
    • R.F. Woods and J.V. McCanny, “A high performance first order IIR Filter chip,” IEE Part D Circuits and Systems, IEE Proc. Part -E, vol. 139, no. 3, pp. 195-202, 1992
    • (1992) IEE Part D Circuits and Systems , vol.139 , Issue.3 , pp. 195-202
    • Woods, R.F.1    McCanny, J.V.2
  • 12
    • 54249096598 scopus 로고
    • The design of a highly pipelined second order IIR filter chip
    • Mar.
    • O.C. McNally, J.V. McCanny, and R.F. Woods, “The design of a highly pipelined second order IIR filter chip,” Int'l J. High Speed Electronics and Systems, A. Fettweis and P. DeWilde, eds., vol. 4, no. 1, pp. 65-84, Mar. 1993.
    • (1993) Int'l J. High Speed Electronics and Systems , vol.4 , Issue.1 , pp. 65-84
    • McNally, O.C.1    McCanny, J.V.2    Woods, R.F.3
  • 14
    • 0026961765 scopus 로고
    • Algorithms and architectures for high performance recursive filters
    • S.E. McQuillan and J.V. McCanny, “Algorithms and architectures for high performance recursive filters,” Application Specific Array Processors, J. Fortes, E. Lee, and T. Meng, eds., pp. 230-244, IEEE CS Press, 1992
    • (1992) Application Specific Array Processors
    • McQuillan, S.E.1    McCanny, J.V.2
  • 15
    • 0027577491 scopus 로고    scopus 로고
    • Systematic design of pipelined recursive filters
    • M. Lapointe, H.T. Huynh, and P. Fortier, “Systematic design of pipelined recursive filters,” IEEE Trans. Computers, vol. 42, no. 4, pp. 413-426.
    • IEEE Trans. Computers , vol.42 , Issue.4 , pp. 413-426
    • Lapointe, M.1    Huynh, H.T.2    Fortier, P.3
  • 18
    • 84938170417 scopus 로고
    • Efficient serial-parallel arrays for multiplication and addition
    • L. Ciminiera and A. Sera, “Efficient serial-parallel arrays for multiplication and addition,” Proc. Seventh Symp. Computer Arithmetic, pp. 28-35, June 1985.
    • (1985) Proc. Seventh Symp. Computer Arithmetic
    • Ciminiera, L.1    Sera, A.2
  • 19
    • 0025519548 scopus 로고
    • Fast multiplication without carry-propagate addition
    • M.D. Ercegovac and T. Lang, “Fast multiplication without carry-propagate addition,” IEEE Trans. Computers, vol. 39, no. 11, pp. 1,385-1,390, 1990.
    • (1990) IEEE Trans. Computers , vol.39 , Issue.11 , pp. 1,385-1,390
    • Ercegovac, M.D.1    Lang, T.2
  • 20
    • 0010863630 scopus 로고
    • A new class of digital division methods
    • J.E. Robertson, “A new class of digital division methods,” IRE Trans. Electronic Computers, vol. 7, pp. 218-222, 1958.
    • (1958) IRE Trans. Electronic Computers , vol.7 , pp. 218-222
    • Robertson, J.E.1
  • 21
    • 0000838021 scopus 로고
    • online arithmetic: A design methodology and applications
    • M.D. Ercegovac and T. Lang, “online arithmetic: A design methodology and applications,” VLSI Signal Processing III, pp. 252-263, 1988.
    • (1988) VLSI Signal Processing III
    • Ercegovac, M.D.1    Lang, T.2
  • 23
    • 84937078021 scopus 로고
    • Signed digit number representations for fast parallel arithmetic
    • A. Avizienis, “Signed digit number representations for fast parallel arithmetic,” IRE Trans. Computers, vol. 10, pp. 389-400, 1961.
    • (1961) IRE Trans. Computers , vol.10 , pp. 389-400
    • Avizienis, A.1
  • 24
    • 51249174024 scopus 로고
    • Fast radix-2 division with quotient-digit prediction
    • M.D. Ercegovac and T. Lang, “Fast radix-2 division with quotient-digit prediction,”/. VLSI Signal Processing, vol. 1, pp. 169-180, 1989.
    • (1989) , vol.1 , pp. 169-180
    • Ercegovac, M.D.1    Lang, T.2
  • 25
    • 84937994175 scopus 로고
    • Higher-radix division using estimates of the divisor and partial remainders
    • DA. Atkins, “Higher-radix division using estimates of the divisor and partial remainders,” IEEE Trans. Computers, vol. 17, no. 10, pp. 925-934, 1968.
    • (1968) IEEE Trans. Computers , vol.17 , Issue.10 , pp. 925-934
    • Atkins, D.A.1
  • 26
    • 0003897941 scopus 로고
    • Digital Signal Processing: A System Design Approach.
    • D.J. DeFatta, J.G. Lucas, and W.S. Hodgkiss, Digital Signal Processing: A System Design Approach. John Wiley & Sons, 1988.
    • (1988)
    • DeFatta, D.J.1
  • 27
    • 0026240993 scopus 로고
    • Saturation circuitry for redundant number based IIR filters
    • R.F. Woods, O.C. McNally, and S.E. McQuillan, “Saturation circuitry for redundant number based IIR filters,” Electronics Letters, vol. 27, no. 21, pp. 1,961-1,963, 1991.
    • (1991) Electronics Letters , vol.27 , Issue.21 , pp. 1,961-1,963
    • Woods, R.F.1
  • 28
    • 84938169093 scopus 로고
    • Wave digital filters: Theory and practice
    • A. Fettweis, L. Gazsi, and K. Meerkotter, “Wave digital filters: Theory and practice,” Proc. 1988 IEEE Int'l Symp. Circuits and Systems.
    • (1988)
    • Fettweis, A.1    Gazsi, L.2
  • 29
    • 4243484180 scopus 로고
    • Algorithms and architectures for high performance arithmetic processors
    • S.E. McQuillan, “Algorithms and architectures for high performance arithmetic processors,” PhD thesis, The Queen's Univ. of Belfast, 1992.
    • (1992) PhD thesis
    • McQuillan, S.E.1
  • 30
    • 84938168472 scopus 로고
    • VLSI implementations for wave digital filtering
    • R.J. Singh, “VLSI implementations for wave digital filtering,” PhD thesis, The Queen's Univ. of Belfast, May 1993
    • (1993) PhD thesis
    • Singh, R.J.1
  • 31
    • 84938165258 scopus 로고    scopus 로고
    • DRA Malvern, England, private communication
    • R. Walke, DRA Malvern, England, private communication.
    • Walke, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.