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Volumn 44, Issue 2, 1995, Pages 234-247

Fault Coverage and Test Length Estimation for Random Pattern Testing

Author keywords

[No Author keywords available]

Indexed keywords

FAULT COVERAGE; OCCUPANCY; TEST LENGTH; URN MODELS; WAITING TIME;

EID: 0029254427     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.364535     Document Type: Article
Times cited : (18)

References (20)
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  • 3
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  • 5
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    • Random pattern testing versus deterministic testing of RAM's
    • May
    • R. David, M. Fuentes, and B. Courtois, “Random pattern testing versus deterministic testing of RAM's,” IEEE Trans. Comput., vol. 38, pp. 637-650, May 1989.
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    • David, R.1    Fuentes, M.2    Courtois, B.3
  • 6
    • 85023357369 scopus 로고
    • Test generation costs analysis and projections
    • P. Goel, “Test generation costs analysis and projections,” in Proc. 17th Design Automat. Conf, 1980, pp. 77-84.
    • (1980) in Proc. 17th Design Automat. Conf , pp. 77-84
    • Goel, P.1
  • 8
    • 0023542286 scopus 로고
    • Predicting fault coverage for random testing of combinational circuits
    • W. K. Huang, M. Lightner, and F. Lombardi, “Predicting fault coverage for random testing of combinational circuits,” in Proc. IEEE Int. Test Conf., 1987, pp. 843-848.
    • (1987) in Proc. IEEE Int. Test Conf. , pp. 843-848
    • Huang, W.K.1    Lightner, M.2    Lombardi, F.3
  • 10
    • 84938167370 scopus 로고
    • Test generation for single stuck-at faults in combinational circuits using binary decision diagrams
    • Southern Illinois University-Carbondale
    • S. Jayaraman, “Test generation for single stuck-at faults in combinational circuits using binary decision diagrams,” Masters Thesis, Dept. of Electrical Engineering, Southern Illinois University-Carbondale, 1993.
    • (1993) Masters Thesis, Dept. of Electrical Engineering
    • Jayaraman, S.1
  • 11
    • 0024054567 scopus 로고
    • On using signature registers as pseudorandom pattern generators in built-in self-testing
    • Aug.
    • K. Kim, D. S. Ha, and J. G. Tront, “On using signature registers as pseudorandom pattern generators in built-in self-testing,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 919-928, Aug. 1988.
    • (1988) IEEE Trans. Computer-Aided Design , vol.7 , pp. 919-928
    • Kim, K.1    Ha, D.S.2    Tront, J.G.3
  • 13
    • 0004550983 scopus 로고
    • PLATO: A tool for computing exact signal probabilities
    • Bombay
    • R. Krieger, “PLATO: A tool for computing exact signal probabilities,” in Proc. 6th Int. Conf. VLSI Design, Bombay, 1993, pp. 65-68.
    • (1993) in Proc. 6th Int. Conf. VLSI Design , pp. 65-68
    • Krieger, R.1
  • 15
    • 0028745897 scopus 로고
    • WRAPTURE: A tool for evaluation and optimization of weights for weighted random pattern testing
    • A. Majumdar, “WRAPTURE: A tool for evaluation and optimization of weights for weighted random pattern testing,” in Proc. ICCD, 1994, pp. 288-291.
    • (1994) in Proc. ICCD , pp. 288-291
    • Majumdar, A.1
  • 16
    • 0021555937 scopus 로고
    • The coverage problem for random testing
    • Y. K. Malaiya and S. Yang, “The coverage problem for random testing,” in Proc. Int. Test Conf., 1984, pp. 237-242.
    • (1984) in Proc. Int. Test Conf. , pp. 237-242
    • Malaiya, Y.K.1    Yang, S.2
  • 17
    • 0026174924 scopus 로고
    • A branching process model for observability analysis of combinational circuits
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    • (1991) in Proc. 28th Design Automat. Conf , pp. 452-457
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  • 18
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    • On random pattern test length
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    • J. Savir and P. H. Bardell, “On random pattern test length,” IEEE Trans. Comput., vol. C-33, pp. 467-474, June 1984.
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  • 19
    • 0025416171 scopus 로고
    • A statistical theory of digital circuit testability
    • Apr.
    • S. C. Seth, V. D. Agrawal, and H. Farhat, “A statistical theory of digital circuit testability,” IEEE Trans. Comput., vol. 39, pp. 582-586, Apr. 1990.
    • (1990) IEEE Trans. Comput. , vol.39 , pp. 582-586
    • Seth, S.C.1    Agrawal, V.D.2    Farhat, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.