메뉴 건너뛰기




Volumn 15, Issue 5, 1994, Pages 160-162

Suppression of the Boron Penetration Induced Si/SiO2 Interface Degradation by Using a Stacked-Amorphous-Silicon Film as the Gate Structure for pMOSFET

Author keywords

[No Author keywords available]

Indexed keywords

BORON; ELECTRONIC PROPERTIES; SEMICONDUCTING SILICON; SUBSTRATES;

EID: 0028422922     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.291600     Document Type: Article
Times cited : (22)

References (8)
  • 1
    • 0022027064 scopus 로고
    • Design tradeoffs between surface and buried-channel FET's
    • G. J. Hu and R. H. Bruce, “Design tradeoffs between surface and buried-channel FET's,” IEEE Trans. Electron Device, vol. 32, pp. 584–588, 1985.
    • (1985) IEEE Trans. Electron Device , vol.32 , pp. 584-588
    • Hu, G.J.1    Bruce, R.H.2
  • 2
    • 0024170834 scopus 로고    scopus 로고
    • Doping of n+ and p+polysilicon in a dual-gate CMOS process
    • in IEDM Tech. Dig.
    • C. Y. Wong. J. Y.-C. Sun, Y. Taur, C. S. Oh, R. Angelucci, and B. Davari, “Doping of n + and p + polysilicon in a dual-gate CMOS process,” in IEDM Tech. Dig., pp. 238–241, 1988.
    • Wong, C.Y.1    Sun, J.2    Taur, Y.3    Oh, C.S.4    Angelucci, R.5    Davari, B.6
  • 4
    • 0025522695 scopus 로고
    • A comprehensive study on p+polysilicon-gate MOSFET's instability with fluorine incorporation
    • J. J. Sung and C. Y. Lu, “A comprehensive study on p + polysilicon-gate MOSFET's instability with fluorine incorporation,” IEEE Trans. Electron Devices, vol. 37, pp. 2312–2321, 1990.
    • (1990) IEEE Trans. Electron Devices , vol.37 , pp. 2312-2321
    • Sung, J.J.1    Lu, C.Y.2
  • 5
    • 0026712574 scopus 로고
    • Fluorine diffusion on a polysilicon garain boundary network in relation to boron penetration from p+ gates
    • H.-H. Tseng, M. Orlowski, P. J. Tobin, and R. L. Hance, “Fluorine diffusion on a polysilicon garain boundary network in relation to boron penetration from p + gates,” IEEE Electron Device Lett., vol. 13, pp. 14–16, 1992.
    • (1992) IEEE Electron Device Lett. , vol.13 , pp. 14-16
    • Tseng, H.-H.1    Orlowski, M.2    Tobin, P.J.3    Hance, R.L.4
  • 6
    • 0003546643 scopus 로고
    • Characterization of ultrathin oxide prepared by low-temperature wafer loading and nitrogen preannealing before oxidation
    • S. L. Wu, C. L. Lee, and T. F. Lei. “Characterization of ultrathin oxide prepared by low-temperature wafer loading and nitrogen preannealing before oxidation,” J. Appl. Phys., vol. 72, pp. 1378–1385, 1992.
    • (1992) J. Appl. Phys. , vol.72 , pp. 1378-1385
    • Wu, S.L.1    Lee, C.L.2    Lei, T.F.3
  • 7
    • 0026623577 scopus 로고
    • High-performancepolysilicon contacted shallow junctions formed by stacked-amorphous-silicon films
    • S. L. Wu, C. L. Lee, and T. F. Lei, “High-performance polysilicon contacted shallow junctions formed by stacked-amorphous-silicon films,” IEEE Electron Device Lett., vol. 13, pp. 23–25, 1992.
    • (1992) IEEE Electron Device Lett. , vol.13 , pp. 23-25
    • Wu, S.L.1    Lee, C.L.2    Lei, T.F.3
  • 8
    • 34250869424 scopus 로고
    • Anomalous CV characteristics of implanted poly MOS structure in n+/p+ dual-gate CMOS technology
    • C. Y. Lu, J. M. Sung, H. C. Kirsch,- S. J. Hillenius, T. E. Smith, and A. Manchanda, “Anomalous CV characteristics of implanted poly MOS structure in n + /p + dual-gate CMOS technology,” IEEE Electron Device Lett., vol. 10, pp. 192–194, 1989.
    • (1989) IEEE Electron Device Lett. , vol.10 , pp. 192-194
    • Lu, C.Y.1    Sung, J.M.2    Kirsch, H.C.3    Hillenius, -S.J.4    Smith, T.E.5    Manchanda, A.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.