Scheduling cells in an input-queued switch

Electronics Letters

Volumn 29, Issue 25, 1993, Pages 2174-2175

  McKeown, N ^a   Varaiya, P ^a   Walrand, J ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Asynchronous transfer mode; Switches

Indexed keywords

ALGORITHMS; ITERATIVE METHODS; QUEUEING THEORY; SCHEDULING; SWITCHES; TELECOMMUNICATION TRAFFIC;

ASYNCHRONOUS TRANSFER MODE; INPUT QUEUED SWITCH; ITERATIVE ROUND ROBIN MATCHING; PARALLEL ITERATIVE MATCHING; SCHEDULING CELLS;

DATA COMMUNICATION SYSTEMS;

EID: 0027913135     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19931459     Document Type: Article

References (6)

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3. OBARA, H.: ‘Optimum architecture for input queueing ATM switches’, Electron. Lett., 1991, 27, pp. 555-557
4. OBARA, H., OKAMOTO, S., and HAMAZUMI, Y.: ‘Input and output queueing ATM switch architecture with spatial and temporal reservation control’, Electron. Lett., 1992, 28, pp. 22-24
5. KAROL, M., ENG, K., and OBARA, H.: ‘Improving the performance of input-queued ATM packet switches’. INFOCOM’ 92, 1992, pp. 110-115
6. ANDERSON, T., OWICKI, S., SAXE, J., and THACKER, C.: ‘High speed switch scheduling for local area networks’. Proc. Fifth Int. Conf. on Architectural Support for Programming Languages and Operating Systems, October 1992, pp. 98-110