-
1
-
-
0042527154
-
An effective ESD awareness training program
-
O. McAteer, “An effective ESD awareness training program,” in EOS/ESD Symp. Proc., 1980.
-
(1980)
EOS/ESD Symp. Proc
-
-
McAteer, O.1
-
4
-
-
0024170254
-
Designing MOS inputs and outputs to avoid oxide failure in the charged device model
-
T. Maloney, “Designing MOS inputs and outputs to avoid oxide failure in the charged device model,” in Proc. 10th EOS/ESD Symp. 1988, 220–227.
-
(1988)
Proc. 10th EOS/ESD Symp
, pp. 220-227
-
-
Maloney, T.1
-
6
-
-
84937349208
-
Determination of threshold failure levels of semiconductor diodes and transistors due to pulse voltages
-
Dec.
-
D.C. Wunsch and R.B. Bell, “Determination of threshold failure levels of semiconductor diodes and transistors due to pulse voltages,” IEEE Trans. Nucl. Sci., vol. NS-15, pp.244-259, Dec. 1968.
-
(1968)
IEEE Trans. Nucl. Sci
, vol.NS-15
, pp. 244-259
-
-
Wunsch, D.C.1
Bell, R.B.2
-
7
-
-
0024124558
-
The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors
-
K.L. Chen, “The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors,” IEEE Trans. Electron Devices, vol. 35, 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
-
-
Chen, K.L.1
-
8
-
-
0021614057
-
A summary of most effective electrostatic protection circuits for MOS memories and their observed failure modes
-
Sept.
-
C. Duvvury, R.N. Rountree, and L.S. White, “A summary of most effective electrostatic protection circuits for MOS memories and their observed failure modes,” in EOS/ESD Symp. Proc., vol. EOS-5, Sept. 1983, pp. 181–184.
-
(1983)
EOS/ESD Symp. Proc
, vol.EOS-5
, pp. 181-184
-
-
Duvvury, C.1
Rountree, R.N.2
White, L.S.3
-
9
-
-
0043028193
-
Snapback induced gate dielectric breakdown in graded junction NMOS transistors
-
S. Shabde, G. Simmons, A. Baluni, and R. Back, “Snapback induced gate dielectric breakdown in graded junction NMOS transistors,” Proc. of the IRPS, p. 176, 1984.
-
(1984)
Proc. of the IRPS, p
, pp. 176
-
-
Shabde, S.1
Simmons, G.2
Baluni, A.3
Back, R.4
-
10
-
-
0022211208
-
ESD design considerations for ULSI
-
Hyslop and L.S. White
-
C. Duvvury, R. Rountree, McPhee, D. Baglee, A. Hyslop and L.S. White, “ESD design considerations for ULSI,” in EOS/ESD Symp. Proc., vol. EOS-7, 1985.
-
(1985)
EOS/ESD Symp. Proc
, vol.EOS-7
-
-
Duvvury, C.1
Rountree, R.2
McPhee, D.3
Baglee, A.4
-
11
-
-
84889872993
-
Thick oxide ESD performance under process variations
-
R. McPhee, C. Duvvury, R. Rountree, and H. Domingos, “Thick oxide ESD performance under process variations,” in EOS/ESD Proc., vol.EOS-8, 1986, 173.
-
(1986)
EOS/ESD Proc
, vol.EOS-8
, pp. 173
-
-
McPhee, R.1
Duvvury, C.2
Rountree, R.3
Domingos, H.4
-
12
-
-
0024861842
-
ESD phenomena in graded junction devices
-
C. Duvvury, R. Rountree, H. Stiegler, T. Polgreen, and D. Corum, “ESD phenomena in graded junction devices,” in Proc. IRPS, 1989, p.71.
-
(1989)
Proc. IRPS
, pp. 71
-
-
Duvvury, C.1
Rountree, R.2
Stiegler, H.3
Polgreen, T.4
Corum, D.5
-
13
-
-
0020205140
-
An analytical breakdown for short-channel MOSFETs
-
Nov.
-
F.-C. Hsu. P.-K. Ko, S. Tam, C. Hu, and R.S. Muller, “An analytical breakdown for short-channel MOSFETs,” IEEE Trans. Electron Devices, vol. ED-29, Nov. 1982.
-
(1982)
IEEE Trans. Electron Devices
, vol.ED-29
-
-
Hsu, F.-C.1
Ko, P.-K.2
Tam, S.3
Hu, C.4
Muller, R.S.5
-
14
-
-
0023018203
-
Electrostatic discharge protection for one micron CMOS devices and circuits
-
K.L. Chen, G. Giles and D.B. Scott, “Electrostatic discharge protection for one micron CMOS devices and circuits.” in IEDM Tech. Dig., 1986.
-
(1986)
IEDM Tech. Dig
-
-
Chen, K.L.1
Giles, G.2
Scott, D.B.3
-
15
-
-
0022563531
-
ESD protection reliability in 1 μm CMOS technologies
-
C. Duvvury, R. McPhee, D. Baglee, and R. Rountree, “ESD protection reliability in 1 μm CMOS technologies,” in Proc. IRPS, 1986, p. 199.
-
(1986)
Proc. IRPS
, pp. 199
-
-
Duvvury, C.1
McPhee, R.2
Baglee, D.3
Rountree, R.4
-
16
-
-
0023310553
-
Titanium disilicide contact resistivity and its impact on l-μm CMOS circuit performance
-
D.B. Scott et al. “Titanium disilicide contact resistivity and its impact on l-μm CMOS circuit performance,” IEEE Trans. Electron Devices, vol. ED-34, p. 562, 1987.
-
(1987)
IEEE Trans. Electron Devices
, vol.ED-34
, pp. 562
-
-
Scott, D.B.1
-
17
-
-
0024174395
-
ESD protection for submicron CMOS circuits: Issues and solutions
-
R. Rountree, “ESD protection for submicron CMOS circuits: Issues and solutions,” in IEDM Tech. Dig., 1988.
-
(1988)
IEDM Tech. Dig
-
-
Rountree, R.1
-
18
-
-
0004538140
-
Input protection design for overall chip reliability
-
C. Duvvury, T. Taylor, J. Lindgren, and S. Kumar, “Input protection design for overall chip reliability,” in EOS/ESD Symp. Proc., vol. EOS-11. 1989.
-
(1989)
EOS/ESD Symp. Proc
, vol.EOS-11
-
-
Duvvury, C.1
Taylor, T.2
Lindgren, J.3
Kumar, S.4
-
19
-
-
0021629272
-
Using SCRs as transient protection structures in integrated circuits
-
L.R. Avery, “Using SCRs as transient protection structures in integrated circuits,” in EOS/ESD Symp. Proc., 1983, pp. 177–180.
-
(1983)
EOS/ESD Symp. Proc
, pp. 177-180
-
-
Avery, L.R.1
-
20
-
-
0024176693
-
A process tolerant input protection circuit for advanced CMOS processes
-
R. Rountree, C. Duvvury, H. Stiegler, and T. Maki, “A process tolerant input protection circuit for advanced CMOS processes,” in EOS/ESD Symp. Proc., vol. EOS-10, 1988.
-
(1988)
EOS/ESD Symp. Proc
, vol.EOS-10
-
-
Rountree, R.1
Duvvury, C.2
Stiegler, H.3
Maki, T.4
-
21
-
-
0025659612
-
A low-voltage triggering SCR for on-chip ESD protection at output and input pads
-
A. Chatterjee and T. Polgreen, “A low-voltage triggering SCR for on-chip ESD protection at output and input pads,” in Proc. VLSI Tech. Symp., 1990.
-
Proc. VLSI Tech. Symp., 1990
-
-
Chatterjee, A.1
Polgreen, T.2
-
23
-
-
0023173825
-
ESD phenomena and protection issues for CMOS output buffers
-
C. Duvvury, R. Rountree, R. McPhee, and Y. Fong, “ESD phenomena and protection issues for CMOS output buffers,” in Proc. IRPS, 1987, p.174.
-
(1987)
Proc. IRPS
, pp. 174
-
-
Duvvury, C.1
Rountree, R.2
McPhee, R.3
Fong, Y.4
-
24
-
-
0000790344
-
Improving the ESD failure threshold of silicided NMOS output transistors by ensuring uniform current flow
-
T. Polgreen and A. Chatterjee, “Improving the ESD failure threshold of silicided NMOS output transistors by ensuring uniform current flow,” in EOS/ESD Symp. Proc., vol. EOS-11, 1989.
-
(1989)
EOS/ESD Symp. Proc
, vol.EOS-11
-
-
Polgreen, T.1
Chatterjee, A.2
-
25
-
-
84941520779
-
Dynamic Gate-coupled NMOS for efficient ESD in
-
C. Duvvury and C. Diaz, “Dynamic Gate-coupled NMOS for efficient ESD in Proc. 1992.
-
(1992)
Proc
-
-
Duvvury, C.1
Diaz, C.2
-
26
-
-
0024122729
-
Internal chip ESD phenomena beyond the protection circuit
-
C. Duvvury, R. Rountree, and O. Adams, “Internal chip ESD phenomena beyond the protection circuit,” IEEE Trans. Electron Devices, vol. 35, pp.2133, 1988.
-
(1988)
IEEE Trans. Electron Devices
, vol.35
, pp. 2133
-
-
Duvvury, C.1
Rountree, R.2
Adams, O.3
-
27
-
-
4244122256
-
Design and simulation of a 4kV ESD protection circuit for a 0.8/xtn BiC-MOS process
-
A. Chatterjee, T. Polgreen, and A. Amerasekera, “Design and simulation of a 4kV ESD protection circuit for a 0.8/xtn BiC-MOS process,” in Tech. Dig. I EDM, 1991, pp.913-916.
-
(1991)
Tech. Dig. I EDM
, pp. 913-916
-
-
Chatterjee, A.1
Polgreen, T.2
Amerasekera, A.3
-
28
-
-
0042152538
-
An investigation of BiC-MOS ESD protection circuit elements and applications in submicron technologies
-
A. Amerasekera and A. Chatterjee, “An investigation of BiC-MOS ESD protection circuit elements and applications in submicron technologies,” in Proc. 14th EOS/ESD Symp., 1992.
-
(1992)
Proc. 14th EOS/ESD Symp
-
-
Amerasekera, A.1
Chatterjee, A.2
-
29
-
-
0026817821
-
ESD failure modes: Characteristics, mechanisms and process influences
-
van Roozendaal, M. Hannemann, P. Schofield
-
A. Amerasekera, W. van den Abeelen, L. van Roozendaal, M. Hannemann, P. Schofield, “ESD failure modes: Characteristics, mechanisms and process influences,” IEEE Trans. Electron Devices, vol. 39, pp. 430–436, 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39
, pp. 430-436
-
-
Amerasekera, A.1
Van den, W.2
Abeelen, L.3
-
30
-
-
0004638157
-
An analysis of low voltage ESD damage in advanced CMOS processes
-
A. Amerasekera, L. van Roozendaal, J. Abderhalden, J. Bruines, and L. Sevat, “An analysis of low voltage ESD damage in advanced CMOS processes,” in Proc. 12th EOS/ESD Symp., 1990, pp. 143–150.
-
(1990)
Proc. 12th EOS/ESD Symp
, pp. 143-150
-
-
Amerasekera, A.1
van Roozendaal, L.2
Abderhalden, J.3
Bruines, J.4
Sevat, L.5
-
31
-
-
0026381814
-
A new ESD protection concept for VLSI CMOS circuits avoiding circuit stress
-
X. Guggenmos and R. Holzner, “A new ESD protection concept for VLSI CMOS circuits avoiding circuit stress,” in Proc. 13th EOS/ESD Symp., 1991, pp. 74–82.
-
(1991)
Proc. 13th EOS/ESD Symp
, pp. 74-82
-
-
Guggenmos, X.1
Holzner, R.2
-
32
-
-
0011159445
-
Process and design optimization for advanced CMOS I/O ESD protection circuits
-
S. Daniel, G. Krieger, “Process and design optimization for advanced CMOS I/O ESD protection circuits,” in Proc. 12th EOS/ESD Symp., 1990, pp. 206–213.
-
(1990)
Proc. 12th EOS/ESD Symp
, pp. 206-213
-
-
Daniel, S.1
Krieger, G.2
-
33
-
-
4243768766
-
Electrothermal simulation tools for analysis and design of ESD protection devices
-
K. Mayaram, J. Chern L. Arledge, and P. Yang, “Electrothermal simulation tools for analysis and design of ESD protection devices,” in Tech. Dig. IEDM, 1991, pp.909-912.
-
(1991)
Tech. Dig. IEDM
, pp. 909-912
-
-
Mayaram, K.1
Chern, J.2
Arledge, L.3
Yang, P.4
-
34
-
-
35148815587
-
Pulse power failure modes in semiconductors
-
D.M. Tasca, “Pulse power failure modes in semiconductors,” IEEE Trans. Nucl. Sci., vol. NS-17, 364–372, 1970.
-
(1970)
IEEE Trans. Nucl. Sci
, vol.NS-17
, pp. 364-372
-
-
Tasca, D.M.1
-
35
-
-
0022953710
-
A lumped element model for simulation of ESD failures in silicided devices
-
D. Scott, G. Giles, and J. Hall, “A lumped element model for simulation of ESD failures in silicided devices,” in Proc. 8th EOS/ESD Symp., 1986, pp.41-47.
-
(1986)
Proc. 8th EOS/ESD Symp
, pp. 41-47
-
-
Scott, D.1
Giles, G.2
Hall, J.3
-
36
-
-
0024176692
-
Electrical overstress testing of a 256K UVEPROM to rectangular and double exponential pulses
-
D. Pierce, W. Shiley, B. D. Mulcahy, K.E. Wagner, and M. Wunder, “Electrical overstress testing of a 256K UVEPROM to rectangular and double exponential pulses,” in Proc. 10th EOS/ESD Symp., 1988, pp.137-146.
-
(1988)
Proc. 10th EOS/ESD Symp
, pp. 137-146
-
-
Pierce, D.1
Shiley, W.2
Mulcahy, B.D.3
Wagner, K.E.4
Wunder, M.5
-
37
-
-
0026220468
-
Characterization and modeling of second breakdown in NMOST’s for the extraction of ESD-related process and design parameters
-
A. Amerasekera, L. van Roozendaal, J. Bruines, and F. Kuper, “Characterization and modeling of second breakdown in NMOST’s for the extraction of ESD-related process and design parameters,” IEEE Trans. Electron Devices, vol. 38, pp. 2161–2168, 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, pp. 2161-2168
-
-
Amerasekera, A.1
van Roozendaal, L.2
Bruines, J.3
Kuper, F.4
-
38
-
-
0025426274
-
Thermal failure in semiconductor devices
-
V. Dwyer, A. Franklin, and D. Campbell, “Thermal failure in semiconductor devices,” Solid State. Elec., vol. 33, pp. 553–560, 1990.
-
(1990)
Solid State. Elec
, vol.33
, pp. 553-560
-
-
Dwyer, V.1
Franklin, A.2
Campbell, D.3
-
40
-
-
84941523287
-
Model of leakage current in LDD output MOSFET due to low-level ESD stress
-
S. Ohtani et al., “Model of leakage current in LDD output MOSFET due to low-level ESD stress,” in EOS/ESD Symp. Proc., 1990.
-
(1990)
EOS/ESD Symp. Proc
-
-
Ohtani, S.1
-
42
-
-
84889233385
-
On latency and the physical mechanisms underlying gate oxide damage during ESD events in n-channel MOSFETs
-
D. Krakauer and K. Mistry, “On latency and the physical mechanisms underlying gate oxide damage during ESD events in n-channel MOSFETs,” in EOS/ESD Symp. Proc., vol. EOS-11, 1989.
-
(1989)
EOS/ESD Symp. Proc
, vol.EOS-11
-
-
Krakauer, D.1
Mistry, K.2
-
43
-
-
0026398861
-
Investigation of latent failures due to ESD in CMOS integrated circuits
-
W. Greason and K. Chum, “Investigation of latent failures due to ESD in CMOS integrated circuits,” in EOS/ESD Symp. Proc., 1991.
-
(1991)
EOS/ESD Symp. Proc
-
-
Greason, W.1
Chum, K.2
-
44
-
-
84941513405
-
EM1 characteristics in in small air gap
-
M. Honda, “EM1 characteristics in in small air gap,” in EOS/ESD Symp. Proc., 1985.
-
(1985)
EOS/ESD Symp. Proc
-
-
Honda, M.1
-
45
-
-
0026368223
-
The characteristics of low-voltage ESD and its threat
-
M. Honda, “The characteristics of low-voltage ESD and its threat,” in EOYESD Symp. Proc., 1991.
-
(1991)
EOYESD Symp. Proc
-
-
Honda, M.1
-
46
-
-
84941494737
-
IC Technology: Where is it going and what it means for the ESD industry
-
L. Avery, “IC Technology: Where is it going and what it means for the ESD industry,” Keynote Address, presented at the EOSESD Symp.as, 1985.
-
(1985)
Keynote Address, presented at the EOSESD Symp.as
-
-
Avery, L.1
|