Electrical Characteristics of Textured Polysilicon Oxide Prepared by a Low-Temperature Wafer Loading and N2 Preannealing Process

IEEE Electron Device Letters

Volumn 14, Issue 3, 1993, Pages 113-114

  Wu, Shye Lin ^a   Lin, Ta Yow ^a   Lee, Chung Len ^a   Lei, Tai Fu ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ELECTRIC PROPERTIES; ELECTRODES; ELECTRON TUNNELING; GRAIN BOUNDARIES; LEAKAGE CURRENTS; NONVOLATILE STORAGE; OXIDES; SEMICONDUCTOR DOPING; THIN FILMS;

LOW TEMPERATURE WAFER LOADING; PREANNEALING PROCESS; TEXTURED POLYSILICON OXIDES (POLYOXIDES);

SEMICONDUCTING FILMS;

EID: 0027560425     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.215128     Document Type: Article

References (4)

1. T. Ono, T. Mori, T. Ajioka, and T. Takayashiki, “Studies of thin poly-Si oxides for E and EPROM, in IEDM Tech. Dig., 1985, pp. 380–383.
2. R. M. Anderson and D. R. Kerr, “Evidence for surface asperity mechanisn of conductivity in oxide grown on polycrystalline silicon,” J. Appl. Phys., vol. 48, pp. 4834–4836, 1977.
3. L. Faraone, “Thermal SiO2 films on n+ polycrystalline silicon: Electrical conduction and breakdown,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1785–1794, 1986.
4. S. L. Wu, C. L. Lee, and T. F. Lei, “Characterization of ultra-thin oxide prepared by low-temperature wafers loading and nitrogen preannealing before oxidation,” J. Appl. Phys., vol. 68, pp. 1378–1385, 1992.