메뉴 건너뛰기




Volumn 39, Issue 7, 1992, Pages 1669-1679

A High-Performance 0.5-μm BiCMOS Technology for Fast 4-Mb SRAM’s

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, CMOS--DESIGN;

EID: 0026899987     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.141233     Document Type: Article
Times cited : (17)

References (11)
  • 1
    • 84939767415 scopus 로고
    • Framed mask poly-buffered LOCOS isolation for submicron VLSI technology
    • Meeting Extended Abstracts
    • B. Y. Nguyen, P. Tobin, M. Lien, M. Woo, J. Leiss, and J. D. Hayden, “Framed mask poly-buffered LOCOS isolation for submicron VLSI technology,” in ECS Spring 1990 Meeting Extended Abstracts, vol. 90–1, p. 614.
    • (1990) ECS Spring , vol.90–1 , pp. 614
    • Nguyen, B.Y.1    Tobin, P.2    Lien, M.3    Woo, M.4    Leiss, J.5    Hayden, J.D.6
  • 2
    • 84914936136 scopus 로고
    • A high-performance half-micrometer generation CMOS technology for fast SRAM’s
    • Apr.
    • J. D. Hayden et al., “A high-performance half-micrometer generation CMOS technology for fast SRAM’s,” IEEE Trans. Electron Devices, vol. 38, pp. 876–886, Apr. 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , pp. 876-886
    • Hayden, J.D.1
  • 5
    • 0024705153 scopus 로고
    • A 20-ps Si bipolar Ic using advanced super self-aligned process technology with collector ion implantation.
    • July
    • S. Konaka, E. Yamamoto, K. Sakuma, Y. Amemiya, and T. Sakai, “A 20-ps Si bipolar Ic using advanced super self-aligned process technology with collector ion implantation.” IEEE Trans. Electron Devices, vol. 36, p. 1370, July 1989.
    • (1989) IEEE Trans. Electron Devices , vol.36 , pp. 1370
    • Konaka, S.1    Yamamoto, E.2    Sakuma, K.3    Amemiya, Y.4    Sakai, T.5
  • 8
    • 84942395616 scopus 로고
    • RS/1, Release 4, BBN Software Products Corporation Cambridge MA Oct.
    • RS/1, Release 4, BBN Software Products Corporation, Cambridge MA, Oct. 1988.
    • (1988)
  • 9
    • 0024891007 scopus 로고
    • Polysilicon emitter technology
    • Sept.
    • P. Ashbum, “Polysilicon emitter technology,” in BCTM Tech. Dig., Sept. 1989, p. 90.
    • (1989) BCTM Tech. Dig. , pp. 90
    • Ashbum, P.1
  • 11
    • 0024123241 scopus 로고
    • Modeling hot-carrier effects in polysilicon emitter bipolar transistors
    • Dec.
    • J. D. Burnett and C. Hu, “Modeling hot-carrier effects in polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. 35, pp. 2238–2244, Dec. 1988.
    • (1988) IEEE Trans. Electron Devices , vol.35 , pp. 2238-2244
    • Burnett, J.D.1    Hu, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.