-
1
-
-
34250869424
-
-
C. Y. Lu et al., “Anomalous C-V characteristics of implanted poly MOS structure in n + /p + dual-gate CMOS technology,’’ IEEE Electron Device Lett., vol. 10, no. 5, pp. 192–194, 1989.
-
(1989)
“ Anomalous C-V characteristics of implanted poly MOS structure in n+/p+dual-gate CMOS technology, ’’ IEEE Electron Device Lett.
, vol.10
, Issue.5
, pp. 192-194
-
-
Lu, C.Y.1
-
2
-
-
0024733873
-
Effect of poly silicon-emitter shape on dopant diffusion in polysilicon-emitter transistors
-
T. I. Kamins, “Effect of poly silicon-emitter shape on dopant diffusion in polysilicon-emitter transistors,” IEEE Electron Device Lett., vol. 10, no. 9, pp. 401–404, 1989.
-
(1989)
IEEE Electron Device Lett.
, vol.10
, Issue.9
, pp. 401-404
-
-
Kamins, T.I.1
-
3
-
-
0025659616
-
Perimeter and plug effects in deep sub-micron polysilicon emitter bipolar transistors
-
J. N. Burghartz et al., “Perimeter and plug effects in deep sub-micron polysilicon emitter bipolar transistors,” in Dig. Tech. Papers, 1990 Symp. on VLSI Tech., 1990, pp. 55–56.
-
Dig. Tech. Papers, 1990 Symp. on VLSI Tech.
, vol.1990
, pp. 55-56
-
-
Burghartz, J.N.1
-
4
-
-
0024648289
-
Advanced single-level polysilicon submicrometer BiCMOS technology
-
M. P. Brassington et al., “Advanced single-level polysilicon submicrometer BiCMOS technology,” IEEE Trans. Electron Devices, vol. 36, no. 4, pp. 712–719, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, Issue.4
, pp. 712-719
-
-
Brassington, M.P.1
-
5
-
-
0024919817
-
An advanced BiCMOS process utilizing ultra-thin silicon epitaxy over arsenic buried layers
-
M. H. El-Diwany et al., “An advanced BiCMOS process utilizing ultra-thin silicon epitaxy over arsenic buried layers,” in IEDM Tech. Dig., 1989, p. 245.
-
(1989)
IEDM Tech. Dig.
, pp. 245
-
-
El-Diwany, M.H.1
-
6
-
-
0025578961
-
Low voltage performance of an advanced CMOS/BiCMOS technology featuring 18 GHz bipolar fT and sub-70 ps CMOS gate delay
-
M. H. El-Diwany et al., “Low voltage performance of an advanced CMOS/BiCMOS technology featuring 18 GHz bipolar fT and sub-70 ps CMOS gate delay,” in IEDM Tech. Dig., 1990, p. 489.
-
(1990)
IEDM Tech. Dig.
, pp. 489
-
-
El-Diwany, M.H.1
-
7
-
-
0026171089
-
An investigation of nonideal base currents in advanced self-aligned, etched polysilicon emitter bipolar transistors
-
A. Chantre et al., “An investigation of nonideal base currents in advanced self-aligned, etched polysilicon emitter bipolar transistors,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1354–1361, 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, Issue.6
, pp. 1354-1361
-
-
Chantre, A.1
-
8
-
-
0018679371
-
Effect of emitter contact on current gain of bipolar devices
-
T. H. Ning and R. D. Isaac, “Effect of emitter contact on current gain of bipolar devices,” in IEDM Tech. Dig., 1979, pp. 473–476.
-
(1979)
IEDM Tech. Dig.
, pp. 473-476
-
-
Ning, T.H.1
Isaac, R.D.2
-
9
-
-
0024011317
-
Increased current gain and suppression of peripheral base currents in silicided self-aligned narrow-width poly-silicon-emitter transistors of an advanced BiCMOS technology
-
May
-
M. H. El-Diwany et al., “Increased current gain and suppression of peripheral base currents in silicided self-aligned narrow-width poly-silicon-emitter transistors of an advanced BiCMOS technology,” IEEE Elect. Device Lett., vol. 9, no. 5, May 1988.
-
(1988)
IEEE Elect. Device Lett.
, vol.9
, Issue.5
-
-
El-Diwany, M.H.1
-
10
-
-
0026108044
-
Process limitations and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices
-
C. Y. Lu et al., “Process limitations and device design tradeoffs of self-aligned TiSi 2 junction formation in submicrometer CMOS devices,” IEEE Trans. Electron Devices, vol. 38, no. 2, pp. 246–254, 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, Issue.2
, pp. 246-254
-
-
Lu, C.Y.1
|