-
1
-
-
0018480027
-
Characteristics and limitations of scaled-down MOSFET's due to two-dimensional field effect
-
H. Masuda, M. Nakai, and M. Kubo, “Characteristics and limitations of scaled-down MOSFET's due to two-dimensional field effect,” IEEE Trans. Electron Devices, vol. ED-26, 980, 1979.
-
(1979)
IEEE Trans. Electron Devices
, vol.ED-26
, Issue.980
-
-
Masuda, H.1
Nakai, M.2
Kubo, M.3
-
2
-
-
0039956433
-
Generalized guide for MOSFET miniaturization
-
J. Brews, W. Fichtner, E. Nicollian, and S. Sze, “Generalized guide for MOSFET miniaturization,” IEEE Electron Device Lett., vol. EDL-1, 1, 1980.
-
(1980)
IEEE Electron Device Lett.
, vol.EDL-1
, Issue.1
-
-
Brews, J.1
Fichtner, W.2
Nicollian, E.3
Sze, S.4
-
3
-
-
0020114911
-
MOS device and technology constraints in VLSI
-
Y. El-Mansy, “MOS device and technology constraints in VLSI,” IEEE Trans. Electron Devices, vol. ED-29, p. 567, 1982.
-
(1982)
IEEE Trans. Electron Devices
, vol.ED-29
, pp. 567
-
-
El-Mansy, Y.1
-
4
-
-
0020832969
-
A re-examination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI
-
H. Shichijo, “A re-examination of practical performance limits of scaled n-channel and p-channel MOS devices for VLSI,” Solid-State Electron., vol. 26, p. 969, 1983.
-
(1983)
Solid-State Electron
, vol.26
, pp. 969
-
-
Shichijo, H.1
-
5
-
-
84939765204
-
Constraints on the application of 0.5 μm MOSFET's to ULSI systems
-
E. Takeda, G. Jones, and H. Ahmed, “Constraints on the application of 0.5 μ m MOSFET's to ULSI systems,” IEEE Trans. Electron Devices, vol. ED-32, 322, 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, Issue.322
-
-
Takeda, E.1
Jones, G.2
Ahmed, H.3
-
6
-
-
0022987950
-
Power supply voltage for future CMOS VLSI in half and sub-micrometer
-
M. Kakumu, M. Kinugawa, K. Hashimoto, and J. Matsunaga, “Power supply voltage for future CMOS VLSI in half and sub micrometer,” in IEDM Tech. Dig., p. 399, 1986.
-
(1986)
IEDM Tech. Dig.
, pp. 399
-
-
Kakumu, M.1
Kinugawa, M.2
Hashimoto, K.3
Matsunaga, J.4
-
7
-
-
0024053491
-
On the performance limit for Si MOSFET's: Experimental study
-
A. Toriumi, M. Iwase, and M. Yoshimi, “On the performance limit for Si MOSFET's: Experimental study,” IEEE Trans. Electron vol. 1988.
-
(1988)
IEEE Trans. Electron
-
-
Toriumi, A.1
Iwase, M.2
Yoshimi, M.3
-
8
-
-
0024918845
-
Performance and hot-carrier reliability of deep-submicrometer CMOS
-
T. Chan and H. Gaw, “Performance and hot-carrier reliability of deep-submicrometer CMOS,” in IEDM Tech. Dig., p. 71, 1989.
-
(1989)
IEDM Tech. Dig.
, pp. 71
-
-
Chan, T.1
Gaw, H.2
-
9
-
-
0023995279
-
Deep-submicrometer MOS device fabrication using a photoresist-ashing technique
-
J. Chung, M. C. Jeng, J. Moon, A. Wu, T. Chan, P. K. Ko, and C. Hu, “Deep-submicrometer MOS device fabrication using a photoresist-ashing technique,” IEEE Electron Device Lett., vol. 9, 1988.
-
(1988)
IEEE Electron Device Lett.
, vol.9
-
-
Chung, J.1
Jeng, M.C.2
Moon, J.3
Wu, A.4
Chan, T.5
Ko, P.K.6
Hu, C.7
-
10
-
-
0018468995
-
A new method to determine effective MOSFET channel length
-
K. Terada and H. Muta, “A new method to determine effective MOSFET channel length,” Japan. J. Appl. Phys., vol. 18, p.
-
Japan. J. Appl. Phys.
, vol.18
-
-
Terada, K.1
Muta, H.2
-
11
-
-
0019057709
-
Experimental derivation of the source and drain resistance of MOS transistors
-
P. Suciu and R. Johnston, “Experimental derivation of the source and drain resistance of MOS transistors,” IEEE Trans. Electron Devices, vol. ED-27, 1846, 1980.
-
(1980)
IEEE Trans. Electron Devices
, vol.ED-27
-
-
Suciu, P.1
Johnston, R.2
-
12
-
-
0021517809
-
A capacitance method to determine channel length for conventional and LDD MOSFET's
-
B. J. Sheu and P. K. Ko, “A capacitance method to determine channel length for conventional and LDD MOSFET's,” IEEE Electron Device Lett., vol. EDL-5, p. 491, 1984.
-
(1984)
IEEE Electron Device Lett.
, vol.EDL-5
, pp. 491
-
-
Sheu, B.J.1
Ko, P.K.2
-
13
-
-
0022561312
-
Sub 100 nm channel length transistors fabricated using X-ray lithography
-
S. Chou, H. Smith, and D. Antoniadis, “Sub 100 nm channel length transistors fabricated using X-ray lithography,” J. Vac. Sci. Technol. B, vol. 4, p. 253, 1986.
-
(1986)
J. Vac. Sci. Technol. B
, vol.4
, pp. 253
-
-
Chou, S.1
Smith, H.2
Antoniadis, D.3
-
14
-
-
0020268159
-
0.15 μm channel-length MOSFET's fabricated using e-beam lithography
-
W. Fichtner, R. Watts, D. Fraser, R. Johnston, and S. Sze, “0.15 μm channel-length MOSFET's fabricated using e-beam lithography,” in IEDM Tech. Dig., 272, 1982.
-
(1982)
IEDM Tech. Dig.
, vol.272
-
-
Fichtner, W.1
Watts, R.2
Fraser, D.3
Johnston, R.4
Sze, S.5
-
15
-
-
84941448723
-
Design and experimental technology for 0.1 μm gate-length low-temperature operation of FET's
-
G. Sai-Halasz, M. Wordeman, D. Kern, E. Ganin, S. Rishton, D. Zicherman, H. Schmid, M. Polcari, H. Ng, P. Restle, T. Chang, and R. Dennard, “Design and experimental technology for 0.1 μ m gate-length low-temperature operation of FET's,” IEEE Electron Device Lett., vol. EDL-8, p. 463, 1987.
-
(1987)
IEEE Electron Device Lett.
, vol.EDL-8
, pp. 463
-
-
Sai-Halasz, G.1
Wordeman, M.2
Kern, D.3
Ganin, E.4
Rishton, S.5
Zicherman, D.6
Schmid, H.7
Polcari, M.8
Ng, H.9
Restle, P.10
Chang, T.11
Dennard, R.12
-
16
-
-
0024610567
-
Subquater-micrometer gate-length p-channel and n-channel MOSFET's with extremely shallow source-drain junctions
-
M. Miyake, T. Kobayashi, and Y. Okazaki, “Subquater-micrometer gate-length p-channel and n-channel MOSFET's with extremely shallow source-drain junctions,” IEEE Trans. Electron vol. 1989.
-
(1989)
IEEE Trans. Electron
-
-
Miyake, M.1
Kobayashi, T.2
Okazaki, Y.3
-
17
-
-
0016113965
-
A simple theory to predict the threshold voltage of short-channel IGFET's
-
L. Yau, “A simple theory to predict the threshold voltage of short-channel IGFET's,” Solid-State Electron., vol. 17, 1059, 1974.
-
(1974)
Solid-State Electron
, vol.17
, Issue.1059
-
-
Yau, L.1
-
18
-
-
0018455052
-
VLSI limitations from drain-induced barrier lowering
-
R. Troutman, “VLSI limitations from drain-induced barrier lowering,” IEEE Trans. Electron Devices, vol. ED-26, p. 461, 1979.
-
(1979)
IEEE Trans. Electron Devices
, vol.ED-26
, pp. 461
-
-
Troutman, R.1
-
19
-
-
84939024013
-
Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis
-
T. Toyabe and S. Asai, “Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis, IEEE J. Solid-State Circuits, vol. SC-14, p. 375, 1979.
-
(1979)
IEEE J. Solid-State Circuits
, vol.SC-14
, pp. 375
-
-
Toyabe, T.1
Asai, S.2
-
20
-
-
0020194040
-
Short-channel MOST threshold voltage model
-
K. Ratnakumar and J. Meindl, “Short-channel MOST threshold voltage model,” IEEE J. Solid-State Circuits, vol. SC-17, p. 937, 1982.
-
(1982)
IEEE J. Solid-State Circuits
, vol.SC-17
, pp. 937
-
-
Ratnakumar, K.1
Meindl, J.2
-
21
-
-
0023542548
-
The impact of gate-induced drain leakage current on MOSFET scaling
-
T. Chan, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” in IEDM Tech. Dig., p. 718, 1987.
-
(1987)
IEDM Tech. Dig.
, pp. 718
-
-
Chan, T.1
Chen, J.2
Ko, P.K.3
Hu, C.4
-
22
-
-
0020904903
-
Device performance degradation due to hot-carrier injection at energies below the Si-SiO2 energy barrier
-
E. Takeda, A. Shimizu, and T. Hagiwara, “Device performance degradation due to hot-carrier injection at energies below the Si-SiO2 energy barrier,” in IEDM Tech. Dig., p. 396, 1983.
-
(1983)
IEDM Tech. Dig.
, pp. 396
-
-
Takeda, E.1
Shimizu, A.2
Hagiwara, T.3
-
23
-
-
0022136252
-
Hot electrons and holes in MOSFET's biased below the Si-SiO2 interfacial barrier
-
E. Sangiorgi, B. Ricco, and P. Olivo, “Hot electrons and holes in MOSFET's biased below the Si-SiO2 interfacial barrier,” IEEE Electron Device Lett., vol. EDL-6, p. 513, 1985.
-
(1985)
IEEE Electron Device Lett.
, vol.EDL-6
, pp. 513
-
-
Sangiorgi, E.1
Ricco, B.2
Olivo, P.3
-
24
-
-
0023018409
-
Reliability of submicron MOSFETs stressed at 77 degree K
-
A. Toriumi, M. Iwase, T. Wada, and K. Taniguchi, “Reliability of submicron MOSFETs stressed at 77 degree K,” in IEDM Tech. Dig., p. 382, 1986.
-
(1986)
IEDM Tech. Dig.
, pp. 382
-
-
Toriumi, A.1
Iwase, M.2
Wada, T.3
Taniguchi, K.4
-
25
-
-
0024172927
-
Hot-electron currents in deep-submicrometer MOSFETs
-
J. Chung, M. C. Jeng, G. May, P. K. Ko, and C. Hu, “Hot-electron currents in deep-submicrometer MOSFETs,” in IEDM Tech. Dig., p. 200, 1988.
-
(1988)
IEDM Tech. Dig.
, pp. 200
-
-
Chung, J.1
Jeng, M.C.2
May, G.3
Ko, P.K.4
Hu, C.5
-
26
-
-
0024860579
-
Low-voltage hot-electron currents and degradation in deep submicrometer MOSFETs
-
J. Chung, M. C. Jeng, J. Moon, P. K. Ko, and C. Hu, “Low-voltage hot-electron currents and degradation in deep submicrometer MOSFETs,” in I nt. Reliability Physics Symp., p. 92, 1989.
-
(1989)
Int. Reliability Physics Symp.
, pp. 92
-
-
Chung, J.1
Jeng, M.C.2
Moon, J.3
Ko, P.K.4
Hu, C.5
-
27
-
-
84945713471
-
Hot-electron-induced MOSFET degradation—Model, monitor, and improvement
-
C. Hu, S. Tam, F. Hsu, P. Ko, T. Chan, and K. Terril, “Hot-electron-induced MOSFET degradation—Model, monitor, and improvement,” IEEE Trans. Electron Devices, vol. ED-32, p. 375, 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, pp. 375
-
-
Hu, C.1
Tam, S.2
Hsu, F.3
Ko, P.4
Chan, T.5
Terril, K.6
-
28
-
-
0019664378
-
A unified model for hot-electron currents in MOSFETs
-
P. K. Ko, R. S. Muller, and C. Hu, “A unified model for hot-electron currents in MOSFETs,” in IEDM Tech. Dig., p. 600, 1981.
-
(1981)
IEDM Tech. Dig.
, pp. 600
-
-
Ko, P.K.1
Muller, R.S.2
Hu, C.3
-
29
-
-
0024126942
-
A study on gate oxide thickness dependence of hot-carrier induced degradation for n-MOSFETs
-
Y. Toyoshima, F. Matsuoka, H. Hayashida, H. Iwai, and K. Kanzaki,” A study on gate oxide thickness dependence of hot-carrier induced degradation for n-MOSFETs,” in VLSI Symp. Dig., p. 39, 1988.
-
(1988)
VLSI Symp. Dig.
, pp. 39
-
-
Toyoshima, Y.1
Matsuoka, F.2
Hayashida, H.3
Iwai, H.4
Kanzaki, K.5
-
30
-
-
0023849054
-
Statical modeling of silicon dioxide reliability
-
J. Lee, I. C. Chen, and C. Hu, “Statical modeling of silicon dioxide reliability,” in Int. Reliability Physics Symp., p. 131, 1988.
-
(1988)
Int. Reliability Physics Symp.
, pp. 131
-
-
Lee, J.1
Chen, I.C.2
Hu, C.3
-
31
-
-
0024170331
-
Projecting the minimum acceptable oxide thickness for time-dependent dielectric breakdown
-
R. Moazzami, J. Lee, I. C. Chen, and C. Hu, “Projecting the minimum acceptable oxide thickness for time-dependent dielectric breakdown,” in IEDM Tech. Dig., p. 710, 1988.
-
(1988)
IEDM Tech. Dig.
, pp. 710
-
-
Moazzami, R.1
Lee, J.2
Chen, I.C.3
Hu, C.4
-
32
-
-
0009599273
-
Characterization of the electron mobility in the inverted < 100) silicon surface
-
A. Sabnis and J. Clemens, “Characterization of the electron mobility in the inverted < 100) silicon surface,” in IEDM Tech. Dig., p. 18, 1979.
-
(1979)
IEDM Tech. Dig.
, pp. 18
-
-
Sabnis, A.1
Clemens, J.2
-
33
-
-
0019048875
-
Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces
-
S. Sun and J. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. ED-27, p. 1497, 1980.
-
(1980)
IEEE Trans. Electron Devices
, vol.ED-27
, pp. 1497
-
-
Sun, S.1
Plummer, J.2
-
34
-
-
0023310827
-
The impact of intrinsic series resistance on MOSFET scaling
-
K. K. Ng and W. T. Lynch, “The impact of intrinsic series resistance on MOSFET scaling,” IEEE Trans. Electron Devices, vol. ED-34, p. 503, 1987.
-
(1987)
IEEE Trans. Electron Devices
, vol.ED-34
, pp. 503
-
-
Ng, K.K.1
Lynch, W.T.2
-
35
-
-
0025519498
-
The effects of source/drain resistance on deep submicrometer device performance
-
M. C. Jeng, J. Chung, P. K. Ko, and C. Hu, “The effects of source/drain resistance on deep submicrometer device performance,” IEEE Trans. Electron Devices, vol. 37, p. 2408, 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, pp. 2408
-
-
Jeng, M.C.1
Chung, J.2
Ko, P.K.3
Hu, C.4
-
36
-
-
0024172244
-
A deep-submicrometer MOSFET model for analog/digital circuit simulations
-
M. C. Jeng, P. K. Ko, and C. Hu, “A deep-submicrometer MOSFET model for analog/digital circuit simulations,” in IEDM Tech. Dig., p. 114, 1988.
-
(1988)
IEDM Tech. Dig.
, pp. 114
-
-
Jeng, M.C.1
Ko, P.K.2
Hu, C.3
-
37
-
-
0021501347
-
The effect of high fields on MOS device and circuit performance
-
C. Sodini, P. K. Ko, and J. Moll, “The effect of high fields on MOS device and circuit performance,” IEEE Trans. Electron Devices, vol. ED-31, p. 1386, 1984.
-
(1984)
IEEE Trans. Electron Devices
, vol.ED-31
, pp. 1386
-
-
Sodini, C.1
Ko, P.K.2
Moll, J.3
-
38
-
-
0024612395
-
A framework to evaluate technology and device design enhancements for MOS integrated circuits
-
C. Sodini, S. Wong, and P. K. Ko, “A framework to evaluate technology and device design enhancements for MOS integrated circuits,” IEEE J. Solid-State Circuits, vol. 24, p. 118, 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 118
-
-
Sodini, C.1
Wong, S.2
Ko, P.K.3
-
39
-
-
0022027064
-
Design tradeoffs between surface and buried channel FET's
-
G. Hu and R. Bruce, “Design tradeoffs between surface and buried channel FET's,” IEEE Trans. Electron Devices, vol. ED-32, p. 584, 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, pp. 584
-
-
Hu, G.1
Bruce, R.2
-
40
-
-
0022329248
-
Reliability and performance of submicron LDD NMOSFETs with buried As nimpurity profiles
-
H. Grinolds, M. Kinugawa, and M. Kakumu, “Reliability and performance of submicron LDD NMOSFETs with buried As nimpurity profiles,” in IEDM Tech. Dig., p. 246, 1985.
-
(1985)
IEDM Tech. Dig.
, pp. 246
-
-
Grinolds, H.1
Kinugawa, M.2
Kakumu, M.3
-
41
-
-
3643120618
-
The impact of n- drain length and gate-drain/source overlap on submicrometer LDD devices for VLSI
-
R. Izawa and E. Takeda, “The impact of n- drain length and gate-drain/source overlap on submicrometer LDD devices for VLSI,” IEEE Electron Device Lett., vol. EDL-8, p. 480, 1987.
-
(1987)
IEEE Electron Device Lett.
, vol.EDL-8
, pp. 480
-
-
Izawa, R.1
Takeda, E.2
-
42
-
-
0023593231
-
Hot carrier induced degradation mode depending on the LDD structure in NMOSFETs
-
A. Yoshida and Y. Ushiku, “Hot carrier induced degradation mode depending on the LDD structure in NMOSFETs,” in IEDM Tech. Dig., p. 42, 1987.
-
(1987)
IEDM Tech. Dig.
, pp. 42
-
-
Yoshida, A.1
Ushiku, Y.2
-
43
-
-
0020112866
-
Fabrication of high-performance LDDFETs with oxide sidewall-spacer technology
-
P. Tsang, W. Walker, J. Shepard, and D. Critchlow, “Fabrication of high-performance LDDFETs with oxide sidewall-spacer technology,” IEEE Trans. Electron Devices, vol. ED-29, p. 590, 1982
-
(1982)
IEEE Trans. Electron Devices
, vol.ED-29
, pp. 590
-
-
Tsang, P.1
Walker, W.2
Shepard, J.3
Critchlow, D.4
|