A 16-ns 1-Mb CMOS EPROM

IEEE Journal of Solid-State Circuits

Volumn 25, Issue 5, 1990, Pages 1141-1146

  Kuriyama, Masao ^a   Atsumi, Shigeru ^a   Imamiya, Ken Ichi ^a   Iyama, Yumiko ^a   Matsukawa, Naohiro ^a   Arak, Httoshi ^a   Narita, Kazuhito ^a   Masuda, Kazunori ^a   Tanaka, Sumio ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE, SEMICONDUCTOR - STORAGE DEVICES; INTEGRATED CIRCUITS, CMOS; SEMICONDUCTOR DEVICES, MOS - DESIGN;

CMOS TECHNOLOGY; EPROM; HIGH-SPEED CIRCUIT TECHNOLOGY;

DATA STORAGE, DIGITAL;

EID: 0025508129     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.62135     Document Type: Article

References (6)

1. D. Hoff et al, “A 23-ns 256K EPROM with double-layer metal and address transition detection,” IEEE J. Solid-State Circuits, vol. 24, 1250–1258, Oct. 1989.
2. S. Atsumi et al, “A 16ns 1Mb CMOS EPROM,” in ISSCC Dig. Tech. Papers, Feb. 1990, 58–59.
3. S. Pathak et al., “A 25ns CMOS EPROM using a 4-transistor cell,” in ISSCC Dig. Tech. Papers, Feb. 1985, pp. 162–163.
4. T. Sakurai et al., “A low power 46ns 256kbit CMOS static RAM with dynamic double word line,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 578–585, Oct. 1984.
5. K. Imamiya et al., “A 68ns 4Mbit CMOS EPROM with high noise immunity design,” in Symp. VLSI Circuit Dig. Tech. Papers, 1989, pp. 37–38.
6. S. Tanaka et al., “A programmable 256K CMOS EPROM with on-chip test circuits” in ISSCC Dig. Tech. Papers, Feb. 1984, pp. 148–149.