Multilevel Logic Minimization Using Implicit Don't Cares

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 7, Issue 6, 1988, Pages 723-740

  Bartlett, Karen A ^a   Brayton, Robert K ^b   Hachtel, Gary D ^c   Jacoby, Reily M ^c   Morrison, Christopher R ^c   Rudell, Richard L ^c   SangiovannI Vincentelli, Alberto ^c   Wang, Albert R ^c  

^a UNIVERSITY OF COLORADO   (United States)

^b Research Center   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER METATHEORY - BOOLEAN FUNCTIONS; LOGIC CIRCUITS - TESTING;

IMPLICIT DON'T CARES; LOGIC CIRCUIT TESTABILITY; MULTI-LEVEL LOGIC MINIMIZATION; OPTIMIZED BOOLEAN NETWORKS;

LOGIC DESIGN;

EID: 0024031894     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.3211     Document Type: Article

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