ADVIS: A Software Package for the Design of Systolic Arrays

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 6, Issue 1, 1987, Pages 33-40

  Moldovan, Dan I ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING - ALGORITHMS; INTEGRATED CIRCUITS, VLSI - COMPUTER AIDED DESIGN; MATHEMATICAL TECHNIQUES - MATRIX ALGEBRA; MATHEMATICAL TRANSFORMATIONS - AUTOMATION;

NUMERICAL ALGORITHMS MAPPING; SEQUENTIAL AND PARALLEL FORM ALGORITHMS; SYSTOLIC ARRAYS DESIGN PACKAGE; VLSI ARRAY MODEL;

COMPUTER SOFTWARE;

EID: 0023089493     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/TCAD.1987.1270243     Document Type: Article

References (11)

1. H. T. Kung and C. E. Leiserson, “Systolic arrays for VLSI,” in Introduction to VLSI Systems, C. A. Mead and L. A. Conway, Eds. Reading, MA: Addison-Wesley, 1980, sec. 8.3.
2. H. T. Kung, “Why systolic architectures,” Computer, vol. 15, pp. 37–46, Jan. 1982.
3. R. H. Kuhn, “Optimization and interconnection complexity for parallel processors, single stage networks and decision trees,” Ph.D. dissertation, Dept. of Computer Science, Univ. Illinois, Urbana-Champaign, Champaign, 1980.
4. L. Johnson, V. Weiser, D. Cohen, and A. L. Davis, “Towards a formal treatment of VLSI arrays,” in Proc. Caltech Conf. on VLSI, Jan. 1981.
5. P. R. Cappello and K. Steiglitz, “Unifying VLSI array designs with geometric transformations,” in Proc. 1983 Conf. on Parallel Processing.
6. P. Quinton, “Automatic synthesis of systolic arrays from uniform recurrent equations,” in Proc. 11th Int. Symp. Computer Architectures.
7. D. I. Moldovan, “On the design of algorithms for VLSI systolic arrays,"Proc. IEEE, vol. 71, pp. 113–120, Jan. 1983.
8. J. A. B. Fortes, “Algorithm transformations for parallel processing and VLSI architecture design,” Ph.D. thesis, Dept. of Electrical Engineering-Systems, USC, Los Angeles, Dec. 1983.
9. D. I. Moldovan, C. I. Wu, and J. A. B. Fortes, “Mapping an arbitrarily large QR algorithm into a fixed size VLSI array,” in Proc. 1984 Conf. on Parallel Processing.
10. Culik and Fris, “Topological transformations as a tool in the design of systolic networks,” TCS, pp. 183–216, 1985.
11. Weiser and Davis, “A wavefront notational tool for VLSI array design,” in VLSI Systems and Computing, H. T. Kung et al. Eds. Rockville, MD: Comp. Science Press, 1981, pp. 226–234.