Modeling of the On-Resistance of LDMOS, VDMOS, and VMOS Power Transistors

IEEE Transactions on Electron Devices

Volumn 27, Issue 2, 1980, Pages 356-367

  Sun, S C ^a   Plummer, James D ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TRANSISTORS;

SEMICONDUCTOR DEVICES, MIS;

EID: 0018985713     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1980.19868     Document Type: Article

References (26)

1. H. J. Sigg, G. D. Vendelin, T. P. Cauge, and J. Kocsis, “D-MOS transistor for microwave applications,” IEEE Trans. Electron Devices, vol. ED-19, pp. 45–53, Jan. 1972.
2. V. A. K. Temple and R. P. Love, “A 600 volt MOSFET with near ideal on resistance,” in IEDM Conf. Dig., pp. 664–666, 1978.
3. M. Nagata, “High-power MOSFETs,” Inst. Phys. Conf., Ser. no. 32, pp. 101–110, 1977.
4. J. D. Plummer and J. D. Meindl, “A monolithic 200-V CMOS analog switch,” IEEE J. Solid-State Circuits, vol. SC-11, no. 6, pp. 809–817, Dec. 1976.
5. Y. Tarui, Y. Hayashi, and T. Sekigawa, “Diffusion self-aligned MOST: A new approach for high speed device,” i n Proc. 1st Conf. on Solid State Devices, Tokyo, 1969, Suppl. to J. Japan. Soc. of Appl. Phys., vol. 39, pp. 105–110, 1970.
6. D. P. Kennedy and R. R. O'Brien, “Analysis of the impurity atom distributon near the diffusion mask for a planar p-n junction,” IBM J. Res. Devel., vol. 9, pp. 179–186, May 1965.
7. M. J. Declercq and J. D. Plummer, “Avalanche breakdown in high-voltage DMOS devices,” IEEE Trans. Electron Devices, vol. ED-23, pp. 1–4, Jan. 1976.
8. F. F. Fang and A. B. Fowler, “Hot electron effects and saturation velocities in silicon inversion layers,” J. Appl. Phys., vol. 41, pp. 1825–1831, Mar. 15, 1970.
9. S. C. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” presented at the IEEE Semiconductor Interface Specialists Conf., New Orleans, LA, Dec. 1979.
10. B. E. Deal, “The current understanding of charges in the thermally oxidized silicon structure,” J. Electrochem. Soc., vol. 121, no. 6, pp. 198C–205C, June 1974.
11. M. D. Pocha, A. G. Gonzalez, and R. W. Dutton, “Threshold voltage controlability in double-diffused-MOS transistors,” IEEE Trans. Electron Devices, vol. ED-21, no. 12, pp. 778–784, Dec. 1974.
12. S. T. Hsu, “Influence of surface states on the measurement of field-effect mobility,” IEEE Trans. Electron Devices, vol. ED-25, no. 11, pp. 1331–1332, Nov. 1978.
13. G. Abowitz, E. Arnold, and E. A. Leventhal, “Surface states and 1/f noise in MOS transistors,” IEEE Trans. Electron Devices, vol. ED-14, no. 11, pp. 775–777, Nov. 1967.
14. C. P. Ho and J. D. Plummer, “Improved MOS device performance through the enhanced oxidation of heavily doped n+ silicon,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 623–630, Apr. 1979.
15. M. D. Pocha and R. W. Dutton, “A computer-aided design model for high-voltage double diffused MOS (DMOS) transistors,” IEEE J. Solid-State Circuits, vol. SC-11, no. 5, pp. 718–726, Oct. 1976.
16. S. L. Miller, “Ionization rates for holes and electrons in silicon,” Phys. Rev., vol. 105, no. 4, pp. 1246–1249, 1957.
17. A. S. Grove, Physics and Technology of Semiconductor Devices. New York: Wiley, 1967.
18. D. M. Caughey and R. E. Thomas, “Carrier mobilities in silicon empirically related to doping and field,” Proc. IEEE (Lett.), vol. 55, pp. 2192–2193, 1967.
19. D. Frohman-Benchkowsky, “On the effect of mobility variation on MOS device characteristics,” Proc. IEEE (Lett.), vol. 56, pp. 217–218, Feb. 1968.
20. S. Ramo, J. R. Whinnery, and T. Van Duzer, Fields and Waves in Communication Electronics. New York: Wiley, 1967, p. 98.
21. B. W. Scharf and J. D. Plummer, “Insulated-gate planar thyristors: II—Quantitative modeling,” this issue, pp. 387–394.
22. A. B. Phillips, Transistor Engineering. New York: McGraw-Hill, 1962, p. 216.
23. H. C. Lin, Integrated Electronics. San Francisco, CA: Holden-Day, 1967, p. 110.
24. V. G. C. Reddi, “Majority carrier surface mobilities in thermally oxidized silicon,” IEEE Trans. Electron Devices, vol. ED-15, no. 3, pp. 151–160, 1968.
25. R. F. David, “Computerized thermal analysis of hybrid circuits,” ECC, pp. 324–332, 1977.
26. D. Sharma, J. Gautier, and G. Merckel, “Negative dynamic resistance in MOS devices,” IEEE J. Solid-State Circuits, vol. SC-13, no. 3, pp. 378–380, June 1978.