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Volumn C-21, Issue 2, 1972, Pages 130-137

Redundancy by Coding Versus Redundancy by Replication for Failure-Tolerant Sequential Circuits

Author keywords

Error correcting circuits; failure tolerant design; majority logic decoding; orthogonizable codes; redundancy techniques

Indexed keywords

COMPUTERS, DIGITAL, RELIABILITY;

EID: 0015300012     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.1972.5008917     Document Type: Article
Times cited : (16)

References (13)
  • 1
    • 0003133883 scopus 로고
    • Probabilistic logics and the synthesis of reliable organisms from unreliable components
    • Princeton, N. J.: Princeton Univ. Press
    •   J. Von Neumann, “Probabilistic logics and the synthesis of reliable organisms from unreliable components,” in Automata Studies (Annals of Mathematical Studies, no. 34). Princeton, N. J.: Princeton Univ. Press, 1956, pp. 43–98.
    • (1956) Automata Studies (Annals of Mathematical Studies, no. 34) , pp. 43-98
    • Von Neumann, J.1
  • 2
    • 85010220420 scopus 로고
    • Reliable circuits using less reliable relays
    • E. F. Moore and C. E. Shannon, “Reliable circuits using less reliable relays,” J. Franklin Inst., vol. 262, pp. 191–208 and 281–297, 1956.
    • (1956) J. Franklin Inst. , vol.262 , pp. 191-208
    • Moore, E.F.1    Shannon, C.E.2
  • 4
    • 84943817322 scopus 로고
    • Error detecting and error correcting codes
    • R. W. Hamming, “Error detecting and error correcting codes,” Bell Syst. Tech. J., vol. 29, pp. 147–160, 1950.
    • (1950) Bell Syst. Tech. J. , vol.29 , pp. 147-160
    • Hamming, R.W.1
  • 5
    • 84944483542 scopus 로고
    • A general method of applying error correction to synchronous digital systems
    • D. B. Armstrong, “A general method of applying error correction to synchronous digital systems,” Bell Syst, Tech. J., vol. 40, pp. 577–593, 1961.
    • (1961) Bell Syst, Tech. J. , vol.40 , pp. 577-593
    • Armstrong, D.B.1
  • 6
    • 0009050701 scopus 로고    scopus 로고
    • Coding techniques for failure-tolerant counters
    • IEEE Trans. Comput.
    • I. S. Reed and A. C. L. Chiang, “Coding techniques for failure-tolerant counters,” IEEE Trans. Comput., vol. C-19, pp. 1035–1038, Nov. 1970.
    • , vol.C-19 , pp. 1035-1038
    • Reed, I.S.1    Chiang, A.C.L.2
  • 7
    • 84939737171 scopus 로고
    • Failure-Tolerant Computer Design
    • W. H. Pierce, Failure-Tolerant Computer Design, New York: Academic Press, 1965, pp. 132–145.
    • (1965) New York: Academic Press , pp. 132-145
    • Pierce, W.H.1
  • 8
    • 9144245836 scopus 로고
    • A class of multiple-error-correcting codes and the decoding scheme
    • Sept.
    • 1. S. Reed, “A class of multiple-error-correcting codes and the decoding scheme,” IRE Trans. Inforn. Theory, vol. IT-4, pp. 38–49, Sept. 1954.
    • (1954) IRE Trans. Inforn. Theory , vol.IT-4 , pp. 38-49
    • Reed, I.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.