Coding Techniques for Failure-Tolerant Counters

IEEE Transactions on Computers

Volumn C-19, Issue 11, 1970, Pages 1035-1038

  Reed, Irving S ^a   Chiang, Albert C L ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b Macrodata Company ^*  (United States)

Author keywords

Failure tolerant counter; Hamming code; majority element; parity check code; Reed Muller code

Indexed keywords

EID: 0009050701     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/T-C.1970.222829     Document Type: Article

References (8)

1. I. S. Reed, “A systematic method for increasing the reliability of sequential circuits,” Technology Service Corp., Santa Monica, Calif., Technical Memo. 2, July 1967 (not generally available).
2. “A class of multiple-error-correcting codes and the decoding scheme,” IRE Trans. Inform. Theory, vol. IT-4, pp. 38–49, September 1954.
3. D. B. Armstrong, “A general method of applying error-correcting to synchronous digital systems,” Bell Syst. Tech. J., vol. 40, pp. 572–593, 1961.
4. W. H. Pierce, Failure-Tolerant Computer Design. New York: Academic Press, 1965.
5. R. W. Hamming, “Error detecting and correcting codes,” Bell Sys. Tech. J., vol. 29, pp. 147–160, 1950.
6. I. S. Reed, T. C. Bartee, and I. L. Lebow, Theory and Design of Digital Machines. New York: McGraw-Hill, 1962.
7. W. W. Peterson, Error-Correcting Codes. Cambridge, Mass.: M.I.T. Press, 1961, ch. 3.
8. R. Ash, Information Theory. New York: Wiley, 1965, ch. 4.