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Volumn 2, Issue , 2001, Pages 765-768

A 1.2V 500MHz 32-bit carry-lookahead adder

Author keywords

[No Author keywords available]

Indexed keywords

CARRY LOOK-AHEAD ADDER; CLOCK FREQUENCY; CMOS TECHNOLOGY; FULL VOLTAGE; FULL-SWING; HIGH SPEED; INTERNAL NODES; LOW-VOLTAGE APPLICATIONS; OPERATION SPEED; POWER DISSIPATION; POWER SUPPLY; SUPPLY VOLTAGES; TRUE-SINGLE-PHASE-CLOCKING;

EID: 0013031309     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (14)
  • 2
    • 0020102009 scopus 로고
    • A regular layout for parallel adders
    • R. P. Brent and H. T. Kung, "A regular layout for parallel adders, " IEEE Trans. Comput., vol. C-31, 1982, pp. 280-284.
    • (1982) IEEE Trans. Comput. , vol.C-31 , pp. 280-284
    • Brent, R.P.1    Kung, H.T.2
  • 4
    • 0024647831 scopus 로고
    • Ultra fast compact 32-bit CMOS adder in multiple-output domino logic
    • I. S. Hwang and A. L. Fisher, "Ultra fast compact 32-bit CMOS adder in multiple-output domino logic, " IEEE J. Solid-state Circuit, vol. 24, 1989, pp. 358-369.
    • (1989) IEEE J. Solid-state Circuit , vol.24 , pp. 358-369
    • Hwang, I.S.1    Fisher, A.L.2
  • 5
    • 0025430517 scopus 로고
    • Area-time optimal adder design
    • B. W. Y. Wei and C. D. Thompson, "Area-time optimal adder design, " IEEE Trans. Comput., vol. 39, 1990, pp. 666-675.
    • (1990) IEEE Trans. Comput. , vol.39 , pp. 666-675
    • Wei, B.W.Y.1    Thompson, C.D.2
  • 7
    • 0025470946 scopus 로고
    • Analysis and design of CMOS Manchesteradders with variable carry-skip
    • P. K. Chan and M. D. F. Schlag, "Analysis and design of CMOS Manchesteradders with variable carry-skip, " IEEE Trans. Comput. vol. 39, 1990, pp. 983-992.
    • (1990) IEEE Trans. Comput. , vol.39 , pp. 983-992
    • Chan, P.K.1    Schlag, M.D.F.2
  • 8
    • 0003290827 scopus 로고
    • A way to build efficient carry skip adders
    • A. Guyot et al., "A way to build efficient carry skip adders, " IEEE Trans.Comput., vol. C-36, 1987, pp. 1144-1151.
    • (1987) IEEE Trans.Comput. , vol.C-36 , pp. 1144-1151
    • Guyot, A.1
  • 9
    • 0001608558 scopus 로고
    • Carry-select adder
    • O. J. Bedrij, "Carry-select adder, " IRE Trans. Elec. Comp., vol. EC-11, 1962, pp.340-346.
    • (1962) IRE Trans. Elec. Comp. , vol.EC-11 , pp. 340-346
    • Bedrij, O.J.1
  • 10
    • 84913396280 scopus 로고
    • Conditional-sum addition logic
    • J. Sklansky, "Conditional-sum addition logic, " IRE Trans. Elec. Comp., vol.EC-9, 1960, pp. 226-231.
    • (1960) IRE Trans. Elec. Comp. , vol.EC-9 , pp. 226-231
    • Sklansky, J.1
  • 11
    • 0026907993 scopus 로고
    • A spanning tree carry lookahead adder
    • T. Lynch and E. E. Swartzlander, "A spanning tree carry lookahead adder, " IEEE Trans. Comput. vol. C-41, 1992, pp. 931-939.
    • (1992) IEEE Trans. Comput. , vol.C-41 , pp. 931-939
    • Lynch, T.1    Swartzlander, E.E.2
  • 12
    • 0002846642 scopus 로고
    • Optimizing arithmetic elements for sigmal processing
    • K, Yao et al, Ed. New York, NY: IEEE
    • T. k. Callway and E. E. Swartzlander, "Optimizing arithmetic elements for sigmal processing, " in VLSI sig. Proc. Vol. V, K, Yao et al, Ed. New York, NY: IEEE, 1992, pp.91-100.
    • (1992) VLSI Sig. Proc. , vol.5 , pp. 91-100
    • Callway, T.K.1    Swartzlander, E.E.2
  • 14
    • 2442529529 scopus 로고    scopus 로고
    • The non-full voltage swing TSPC (NSTSPC) logic design
    • Hotel Shilla Cheju Cheju, Korea August 28-30
    • Kuo-Hsing Cheng, and Yung-Chong Huang, "The Non-full Voltage Swing TSPC (NSTSPC) Logic Design, " Proceedings of The Second IEEE Asia Pacific Conference on ASICs, Hotel Shilla Cheju Cheju, Korea August 28-30, 2000 pp.37-40.
    • (2000) Proceedings of the Second IEEE Asia Pacific Conference on ASICs , pp. 37-40
    • Cheng, K.-H.1    Huang, Y.-C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.