3.5 NS, 64 bit, carry-lookahead adder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 1996, Pages 297-300

  Dozza, Davide ^a   Gaddoni, Marco ^a   Baccarani, Giorgio ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BACKPROPAGATION; CARRY LOGIC; CELLULAR ARRAYS; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; MULTIPLEXING EQUIPMENT; MULTIPLYING CIRCUITS; NUMERICAL METHODS; OPTIMIZATION;

BINARY TREE STRUCTURE; CARRY LOOKAHEAD ADDERS; CMOS TECHNOLOGY; DOMINO LOGIC; POWER DISSIPATION;

ADDERS;

EID: 0029696942     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)