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Volumn 88, Issue 7, 2001, Pages 779-787

New symmetrical buffer design for VLSI applications

Author keywords

[No Author keywords available]

Indexed keywords


EID: 0012931518     PISSN: 00207217     EISSN: None     Source Type: Journal    
DOI: 10.1080/00207210110058148     Document Type: Article
Times cited : (7)

References (11)
  • 1
    • 1842696605 scopus 로고
    • Symmetrical output complementary buffer. US Patent 4617477
    • DEPAOLIS, M. V., 1986, Symmetrical output complementary buffer. US Patent 4617477.
    • (1986)
    • Depaolis, M.V.1
  • 2
    • 1842797426 scopus 로고
    • Complementary signal output circuit with reduced skew. US Patent 4950920
    • HARA, H., and UENO, M., 1990, Complementary signal output circuit with reduced skew. US Patent 4950920.
    • (1990)
    • Hara, H.1    Ueno, M.2
  • 8
    • 0038670909 scopus 로고
    • Elimination of process-dependent clock skew in CMOS VLSI
    • SHOJI, M., 1986, Elimination of process-dependent clock skew in CMOS VLSI. IEEE Journal of Solid-State Circuits, 21, 875-880.
    • (1986) IEEE Journal of Solid-State Circuits , vol.21 , pp. 875-880
    • Shoji, M.1
  • 9
    • 0003536663 scopus 로고
    • Englewood Cliffs, NJ: Prentice-Hall
    • SHOJI, M., 1988, CMOS digital circuit technology (Englewood Cliffs, NJ: Prentice-Hall), pp. 383-389.
    • (1988) CMOS Digital Circuit Technology , pp. 383-389
    • Shoji, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.