Optimized architecture and design of an output-queued CMOS switch chip

Proceedings - International Conference on Computer Communications and Networks, ICCCN

Volumn 2001-January, Issue , 2001, Pages 448-453

  Luijten, R P ^a   Abel, F ^a   Gusat, M ^a   Minkenberg, C ^a  

^a IBM RESEARCH ZURICH   (Switzerland)

Author keywords

Bandwidth; CMOS technology; Design optimization; Packet switching; Registers; Routing; Scalability; Switches; Throughput; Wiring

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPLEX NETWORKS; COMPUTER NETWORKS; ELECTRIC WIRING; INTEGRATED CIRCUIT DESIGN; NETWORK ARCHITECTURE; PACKET SWITCHING; SCALABILITY; STATIC RANDOM ACCESS STORAGE; SWITCHES; SWITCHING SYSTEMS; THROUGHPUT;

AGGREGATE DATUM; CMOS TECHNOLOGY; DESIGN OPTIMIZATION; OPTIMIZED ARCHITECTURES; REGISTERS; ROUTING; SWITCH ARCHITECTURES; VIRTUAL OUTPUT QUEUING SWITCHES;

MEMORY ARCHITECTURE;

EID: 0012392776     PISSN: 10952055     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCCN.2001.956303     Document Type: Conference Paper

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