Modeling stresses in ultra-thin flip chips

4th International Conference on Adhesive Joining and Coating Technology in Electronics Manufacturing, Proceedings - Presented at Adhesives in Electronics 2000

Volumn , Issue , 2000, Pages 24-27

  Marjamaki P ^a   Reinikainen, T ^b   Kivilahti, J ^a  

^a AALTO UNIVERSITY   (Finland)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

Assembly; Compressive stress; Elasticity; Flip chip; Laboratories; Production; Silicon; Soldering; Thermal stresses; Viscosity

Indexed keywords

ASSEMBLY; CHIP SCALE PACKAGES; COATINGS; COMPRESSIVE STRESS; ELASTICITY; ELECTRONICS PACKAGING; JOINING; LABORATORIES; MANUFACTURE; PRODUCTION; SILICON; SOLDERING; SPARK PLUGS; THERMAL STRESS; VISCOSITY;

CHIP THICKNESS; EXPECTED LIFETIME; FLIP CHIP; FLIP CHIP ASSEMBLIES; LIFE EXPECTANCIES; NORMAL STRESS; RELIABILITY PROBLEMS; SOLDER JOINTS;

FLIP CHIP DEVICES;

EID: 0011587020     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ADHES.2000.860567     Document Type: Conference Paper

References (5)

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3. K. Lodge, D. Pedder: "The Impact of Packaging on the Reliability of Flip-Chip Solder Bonded Devices"; IEEE Transactions on Components, Hybrids and Manufacturing Technology, vol. 13, n. 4, Dec 1990
4. J. Wang, Z. Qian, S. Liu: "Process Induced Stresses of a Flip-Chip Packaging by Sequential Processing Modeling Technique"; Journal of Electronic Packaging, vol. 120, Sep 1998
5. P. Winter, E. Wallach: "Microstructural Modelling and Electronic Interconnect Reliability"; Soldering & Surface Mount Technology, n. 26, July 1997