FPGA based on-line complex-number multipliers

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2001, Pages 1481-1484

  Perez Pascual A ^a   Sansaloni, T ^a   Valls, J ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

DISTRIBUTED ARITHMETIC; RADIX 2; REDUNDANT NUMBER SYSTEM; SIGNED-DIGIT REPRESENTATION;

FILTER BANKS;

EID: 0009616220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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