A VLSI scan-chain optimization algorithm for multiple scan-paths

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E82-A, Issue 11, 1999, Pages 2499-2504

  Kobayashi, Susumu ^a   Edahiro, Masato ^b   Kubo, Mikio ^b  

^a NEC CORPORATION   (Japan)

^b TOKYO UNIVERSITY OF MARINE SCIENCE AND TECHNOLOGY   (Japan)

Author keywords

Design for testability; Layout design; Scan chain; VLSI CAD

Indexed keywords

EID: 0008461715     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

1. V. D. Agrawal K.-T. Cheng D. D. Johnson and T. Lin Designing circuits with partial scan IEEE Design & Test of Computer pp.8-15 April 1988.
2. C.-S. Chen K.-H. Lin and T.T. Hwang Layout driven selecting and chaining of partial scan flip-flops Proc. Design Automation Conference pp.2G2-2G7 1996.
3. F. Glover Tabu search I ORSA Journal of Computing vol.1 pp.190-200 1989.
4. F. Glover Tabu search II ORSA Journal of Computing vol.2 pp.4-32 1989.
5. A.V. Goldberg An efficient implementation of a scaling minimum-cost flow algorithm Technical Report STAN-CS92-1439 Computer Science Department Stanford University Stanford CA 1992.
6. D. S. Johnson Local optimization and the traveling salesman problem Proc. 17-th Colloquium on Automata Language Programming pp.44G-4Gl Springer-Verlag 1990.
7. E. L. Lawler J. K. Lenstra A. H. G. Rinnooy Kan and D. B. Shmoys eds. The Traveling Salesman Problem John Wiley & Sons 1985.